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R61505U
262,144-color, 240RGB x 320 dot graphics liquid crystal controller driver for Amorphous-Silicon TFT Panel
REJxxxxxxx-xxxx Rev.1.21 April 9, 2007
Description ......................................................................................................... 6 Features ......................................................................................................... 7
Difference between R61505 and R61505U................................................................................................................. 10
Block Diagram .................................................................................................... 11 Block Function .................................................................................................... 12
1. System Interface .................................................................................................................................................... 12 2. External Display Interface (RGB, VSYNC interfaces) ....................................................................................... 13 3. Address Counter (AC) ........................................................................................................................................... 13 4. Graphics RAM (GRAM) ....................................................................................................................................... 14 5. Grayscale Voltage Generating Circuit ................................................................................................................. 14 6. Liquid crystal drive power supply circuit ............................................................................................................. 14 7. Timing Generator .................................................................................................................................................. 14 8. Oscillator (OSC) .................................................................................................................................................... 14 9. Liquid crystal driver Circuit.................................................................................................................................. 14 10. Internal logic power supply regulator .................................................................................................................. 14
Pin Function ........................................................................................................ 15 PAD arrangement................................................................................................ 22 PAD coordinates ................................................................................................. 24 BUMP arrangement ............................................................................................ 39 Connection example............................................................................................ 40 GRAM address map ............................................................................................ 41 Instruction ......................................................................................................... 43
Outline .......................................................................................................................................................................... 43 Instruction Data Format ............................................................................................................................................. 43 Index (IR) ..................................................................................................................................................................... 44 Display control ............................................................................................................................................................. 44 Device code read (R00h)........................................................................................................................................ 44
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R61505U
Driver Output Control (R01h)................................................................................................................................45 LCD Driving Wave Control (R02h) .......................................................................................................................45 Entry Mode (R03h) .................................................................................................................................................46 Resizing Control (R04h) .........................................................................................................................................49 Display Control 1 (R07h) .......................................................................................................................................50 Display Control 2 (R08h) .......................................................................................................................................52 Display Control 3 (R09h) .......................................................................................................................................53 Display Control 4 (R0Ah).......................................................................................................................................55 External Display Interface Control 1 (R0Ch)........................................................................................................55 Frame Marker Position (R0Dh) .............................................................................................................................57 VCOM Low Power Control (R0Eh) .......................................................................................................................58 External Display Interface Control 2 (R0Fh) ........................................................................................................59 Power control ...............................................................................................................................................................60 Power Control 1 (R10h) .........................................................................................................................................60 Power Control 2 (R11h) .........................................................................................................................................62 Power Control 3 (R12h) .........................................................................................................................................64 Power Control 4 (R13h) .........................................................................................................................................66 Power Control 5 (R17h) .........................................................................................................................................66 Power Control 6 (R19h) .........................................................................................................................................67 RAM access instruction ...............................................................................................................................................68 RAM Address Set (Horizontal Address) (R20h) RAM Address Set (Vertical Address) (R21h) ............................68 Write Data to GRAM (R22h)..................................................................................................................................69 Read Data from GRAM (R22h) ..............................................................................................................................72 NVM(NON-VOLATILE MEMORY) write control instruction.................................................................................73 NVM read data (R28h), VCOM High Voltage (R29h, R2Ah)................................................................................73
Control .......................................................................................................................................................................76 Control 1 ~ 14 (R30h to R3Dh) ...........................................................................................................................76
Window address control instruction............................................................................................................................78 Window Horizontal RAM Address Start/End (R50h/ R51h) ..................................................................................78 Window Vertical RAM Address Start/End (R52h/R53h) .......................................................................................78 Base image display control instruction .......................................................................................................................79 Driver Output Control (R60h),...............................................................................................................................79 Base Image Display Control (R61h) ......................................................................................................................79 Vertical Scroll Control (R6Ah)...............................................................................................................................79 Partial display control instruction...............................................................................................................................82 Partial Image 1: Display Position (R80h), RAM Address (Start/End Line Address) (R81h/R82h)......................82 Partial Image 2: Display Position (R83h), RAM Address (Start/End Line Address) (R84h/R85h)......................82 Panel interface control instruction .............................................................................................................................83 Panel interface control 1(R90h).............................................................................................................................83 Panel interface control 2(R92h).............................................................................................................................85 Panel interface control 3(R93h).............................................................................................................................86 Panel interface control 4(R95h).............................................................................................................................87 Panel interface control 5(R97h).............................................................................................................................89 Panel interface control 6(R98h).............................................................................................................................89 NVM(NON-VOLATILE MEMORY) control .............................................................................................................90 NVM access control 1 (RA0h), NVM access control 2 (RA1h) .............................................................................90 Calibration control (RA4h) ....................................................................................................................................91 Setting disabled instruction (Inhibition).....................................................................................................................92
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R61505U
Instruction List .................................................................................................... 93 Reset Function..................................................................................................... 94 Basic mode operation of the R61505U ............................................................... 96 Interface and data format .................................................................................... 97 System Interface.................................................................................................. 100
80-system 18-bit Bus Interface .................................................................................................................................... 101 80-system 16-bit Bus Interface .................................................................................................................................... 102 Data Transfer Synchronization in 16-bit Bus Interface operation ........................................................................... 104 80-system 9-bit Bus Interface ...................................................................................................................................... 105 Data Transfer Synchronization in 9-bit Bus Interface operation ............................................................................. 106 80-system 8-bit Bus Interface ...................................................................................................................................... 107 Data Transfer Synchronization in 8-bit Bus Interface operation ............................................................................. 109 Serial Interface............................................................................................................................................................. 110
VSYNC Interface ................................................................................................ 113
Notes to VSYNC Interface operation .......................................................................................................................... 115
FMARK Interface ............................................................................................... 117
FMP setting example ................................................................................................................................................... 120
External Display Interface................................................................................... 121
RGB Interface .............................................................................................................................................................. 122 Polarities of VSYNC, HSYNC, ENABLE, and DOTCLK Signals ............................................................................ 122 RGB Interface Timing ................................................................................................................................................. 123 16-/18-bit RGB Interface Timing ........................................................................................................................... 123 6-bit RGB Interface Timing.................................................................................................................................... 124 RAM access via system interface in RGB interface operation .................................................................................. 125 6-bit RGB interface ...................................................................................................................................................... 127 Data Transfer Synchronization in 6-bit Bus Interface operation ............................................................................. 128 16-bit RGB interface .................................................................................................................................................... 129 18-bit RGB interface .................................................................................................................................................... 130 Notes to external display interface operation ............................................................................................................. 131
RAM Address and Display Position on the Panel .............................................. 133
Restrictions in setting display control instruction...................................................................................................... 134 Instruction setting example ......................................................................................................................................... 136
Resizing function ................................................................................................ 138
Resizing setting............................................................................................................................................................. 139 Example of 1/2 resizing ............................................................................................................................................... 140 Resizing instruction ..................................................................................................................................................... 140 Notes to Resizing function ........................................................................................................................................... 141
High-speed RAM Write Function ....................................................................... 142
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R61505U
Notes to high-speed RAM write function....................................................................................................................143 High-speed RAM data write in a window address area .............................................................................................144
Window Address Function ................................................................................. 145 Scan Mode Setting .............................................................................................. 146 8-color Display Mode ......................................................................................... 147 Line Inversion AC Drive .................................................................................... 148
Alternating Timing.......................................................................................................................................................149
Frame-Frequency Adjustment Function ............................................................. 150
Relationship between liquid crystal drive duty and frame frequency .......................................................................150
Partial Display Function ..................................................................................... 151 Liquid crystal panel interface timing .................................................................. 152
Internal clock operation...............................................................................................................................................152 RGB interface operation..............................................................................................................................................153
Oscillator
......................................................................................................... 154
Correction function .......................................................................................... 155
Correction registers ...................................................................................................................................................155 Correction register settings and curve relationship ..............................................................................................157
Power-supply Generating Circuit ....................................................................... 158
Power supply circuit connection example 1 (VCI1 = VCIOUT) ...............................................................................158 Power supply circuit connection example 2 (VCI1 = VCI direct input) ...................................................................159
Specifications of Power-supply Circuit External Elements................................ 160 Voltage Setting Pattern Diagram ........................................................................ 161
Liquid crystal application voltage waveform and electrical potential.......................................................................162
VCOMH voltage adjustment sequence............................................................... 163 NVM control sequence ....................................................................................... 165
NVM Write In Sequence..............................................................................................................................................166 NVM Read Out Sequence ............................................................................................................................................167
Power supply Instruction Setting ........................................................................ 169 Notes to Power Supply ON sequence ................................................................. 170 Instruction setting................................................................................................ 171
Display ON/OFF sequences ........................................................................................................................................171
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R61505U
Sleep mode SET/EXIT sequences ............................................................................................................................... 172 Deep standby mode IN/EXIT sequences..................................................................................................................... 173 8-color mode setting..................................................................................................................................................... 176 Partial display setting................................................................................................................................................... 176
Absolute Maximum Ratings ............................................................................... 177 Electrical Characteristics..................................................................................... 178
DC characteristics (VCC= 2.50V~3.30VIOVCC=1.65V~3.30VTa=-40C~+85C See note 1)...................... 178 Step-Up Circuit Characteristics............................................................................................................................. 180 Internal Reference Voltage (Condition: VCC= 2.50V3.30V, Ta=25)........................................................... 180 AC Characteristics ....................................................................................................................................................... 181 1. Clock Characteristics ......................................................................................................................................... 181 2. 80-System Bus Interface Timing Characteristics (18-/ 16- bit interface) ....................................................... 181 3. 80-System Bus Interface Timing Characteristics (9-/ 8- bit interface) ............................................................. 183 4. Clock-synchronized Serial Interface Timing Characteristics............................................................................ 184 5. Reset Timing Characteristics (IOVCC=1.65~3.30V)........................................................................................ 184 6. RGB Interface Timing Characteristics .............................................................................................................. 185 7. LCD driver Output Characteristics ................................................................................................................... 186 Notes on Electrical Characteristics ....................................................................................................................... 187
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R61505U
Description
The R61505U is a single-chip liquid crystal controller driver LSI for a-Si TFT panel, comprising RAM for a maximum 240 RGB x 320 dot graphics display, source driver, gate driver and power supply circuit. For efficient data transfer, the R61505U supports high-speed interface via 8-/9-/16-/18-bit ports as system interface to the microcomputer and high-speed RAM write function. The R61505U supports RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, DB17-0). The power supply circuit incorporates step-up circuit and voltage follower circuit to generate TFT liquid crystal panel drive voltages. The R61505U's power management functions such as 8-color display and deep standby and so on make this LSI an ideal driver for the medium or small sized portable products with color display systems such as digital cellular phones or small PDAs, where long battery life is a major concern.
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R61505U
Features
* * A single-chip controller driver incorporating a gate circuit and a power supply circuit for a maximum 240RGB x 320dots graphics display on amorphous TFT panel in 262k colors System interface - High-speed interfaces via 8-, 9-, 16-, 18-bit parallel ports - Clock synchronous serial interface Moving picture display interface - 6-, 16-, 18-bit RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, DB17-0) - VSYNC interface (System interface + VSYNC) - FMARK interface (System interface + FMARK) High-speed RAM write function Window address function to specify a rectangular area in the internal RAM to write data Write data within a rectangular area in the internal RAM via moving picture interface Reduce data transfer by specifying the area in the RAM to rewrite data Enable displaying the data in the still picture RAM area with a moving picture simultaneously Resizing function (x 1/2, x 1/4) Abundant color display and drawing functions - Programmable -correction function for 262k-color display - Partial display function Low -power consumption architecture (allowing direct input of interface I/O power supply) - Deep standby function - 8-color display function - Input power supply voltages: VCC = 2.5V ~ 3.3 V (logic regulator power supply) IOVCC = 1.65V ~ 3.3 V (interface I/O power supply) VCI = 2.5V ~ 3.3 V (liquid crystal analog circuit power supply) Incorporates a liquid crystal drive power supply circuit - Source driver liquid crystal drive/VCOM power supply: DDVDH-GND = 4.5V ~ 6.0 V VCL-GND = -1.9V ~ -3.0V VCI-VCL 6.0V - Gate drive power supply: VGH-GND = 10.0V ~ 20.0 V VGL-GND = -4.5V ~ -13.5V VGH-VGL 28.0V - VCOM drive (VCOM power supply): VCOMH = 3.0V ~ (DDVDH-0.5)V VCOML = (VCL+0.5)V ~ 0V VCOMH-VCOML amplitude = 6.0V (max.) Liquid crystal power supply startup sequencer TFT storage capacitance: Cst only (common VCOM formula) 172,800-byte internal RAM Internal 720-channel source driver and 320-channel gate driver Single-chip solution for COG module with the arrangement of gate circuits on both sides of the glass substrate Internal NVM: User identification code, 4 bits, VCOM level adjustment, 5 bits x 2 sets
*
* * * * * * *
*
*
* * * * * *
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R61505U * Internal reference voltage: to generate VREG1OUT (VCIR)
Product Numbers * The R61505U has two variations of frequencies enabling users to choose whichever suitable for display system.
Product Number R61505U0 R61505U1 RC Oscillation Frequency 376KHz 600KHz
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R61505U *
No. 1 2 3 4
Power supply specifications
Item TFT data lines TFT gate lines TFT display storage capacitance Liquid crystal drive output S1~S720 G1~320 VCOM R61505U 720 320 Cst only (Common VCOM formula) V0 ~ V31 grayscales VGH-VGL Change VCOMH-VCOML amplitude with electronic volume Change VCOMH with either electronic volume or from VCOMR
Table 1
5
Input voltage
IOVCC (interface voltage)
1.65V ~ 3.30V Power supply to IM0/ID, IM1-3, RESET*, DB17-0, RD*, SDI, SDO, WR/SCL, RS, CS*, VSYNC, HSYNC, DOTCLK, ENABLE, FMARK Connect to VCC and VCI on the FPC when the electrical potentials are the same.
VCC (logic regulator power supply) VCI (liquid crystal drive power supply voltage) VPP (NVM power supply)
2.50V ~ 3.30V Connect to IOVCC and VCI on the FPC when the electrical potentials are the same. 2.50V ~ 3.30V Connect to IOVCC and VCC on the FPC when the electrical potentials are the same. VPP1: 9.00.1V VPP2: 7.50.1V VPP3A/ VPP3B: GND 4.5V ~ 6.0V 10.0V ~ 20.0V -4.5V ~ -13.5V Max. 28.0V -1.9V ~ -3.0V Max. 6.0V VCI1 x 2, x 3 VCI1 x 6, x 7, x 8 VCI1 x -3, x -4, x -5 VCI1 x -1
6
Liquid crystal drive voltages
DDVDH VGH VGL VGH-VGL VCL VCI-VCL
6
Internal step-up circuits
VLOUT1 (DDVDH) VLOUT2 (VGH) VLOUT3 (VGL) VCL
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R61505U Difference between R61505 and R61505U Table 2 R61505
BT[2:0] 3'h0 DDVDH VCI1 x 2 [x 2] VCL -VCI1 [x -1] VGH DDVDH x 4 [x 8] VGL -(VCI1+DDVDH x 2) [x -5] Capacitor connection pins VLOUT1, VLOUT2, VLOUT3, VCL, C11, C12, C13, C21 , C22, C23
Table 3 R61505U
BT[2:0] 3'h0 DDVDH VCI1 x 2 [x 2] VCL -VCI1 [x -1] VGH DDVDH x 3 [x 6] VGL -(VCI1+DDVDH x 2) [x -5] Capacitor connection pins See "Specifications of Powersupply Circuit External Elements". C23may be omitted.
Table 4 VCOM amplitude
R61505 VCOM amplitude (Max.) VREG1OUT x 1.0 R61505U VREG1OUT x 1.24
Table 5 Oscillator
R61505 RC Oscillation External resistor R61505U Internal resistor
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R61505U
Block Diagram
RGND GND
Index register (IR)
Control register (CR)
AGND
Address counter
IOGND
IOVCC
IM3-1,IM0/ID
Source line drive circuit
System interface
18-bit 16-bit 9-bit 8-bit Serial
18
M alternating timing
CS* RS WR/SCL RD* SDI SDO DB0-17
BGR circuit
18
Write data 18 latch
18
Latch circuit
Latch circuit
Latch circuit
Graphics RAM (GRAM) 172,800 bytes
S1-720
Read data latch
VSYNC HSYNC DOTCLK ENABLE
External display interface
V31-0 VSYNC HSYNC DOTCLK ENABLE DB17-0
timing generator
VGS VTEST V0T V31T VMON
-correction circuit
grayscale voltage generating circuit
RESET* FMARK TS8-0 TSC
scan data generating circuit
gate line drive circuit
CPG
G1-G320
Internal reference voltage generating circuit
VCC
Internal logic power supply regulator
VPP1-3 TEST1 TEST2 TEST3 TEST4 TEST5 VREFC VRTEST VREF VDDTEST VREFD
VDD
Liquid crystal drive level generating circuit
VREG1OUT
VLOUT1 DDVDH
C11+/C11C12+/C12C13+/C13C21+/C21-
C22+/C22C23+/C23-
VcomR
VCI1
VcomH
Vcom
VLOUT2 VGH VLOUT3 VGL
VCIOUT
VcomL
VCL
Figure 1
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TESTA5
VCI
VCILVL
R61505U
Block Function
1. System Interface
The R61505U supports 80-system high-speed interface via 8-, 9-, 16-, 18-bit parallel ports and a clock synchronous serial interface. The interface is selected by setting the IM3-0 pins. The R61505U has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR). The IR is the register to store index information from control register and internal GRAM. The WDR is the register to temporarily store data to be written to control register and internal GRAM. The RDR is the register to temporarily store the data read from the GRAM. The data from the MPU to be written to the internal GRAM is first written to the WDR and then automatically written to the internal GRAM in internal operation. The data is read via RDR from the internal GRAM. Therefore, invalid data is sent to the data bus when the R61505U performs the first read operation from the internal GRAM. Valid data is read out when the R61505U performs the second and subsequent read operation. The instruction execution time except that of starting oscillation takes 0 clock cycle to allow writing instructions consecutively. Table 6 Register Selection (80-system 8/9/16/18-bit Parallel Interface)
WR* 0 1 0 1 RD* 1 0 1 0 RS 0 0 1 1 Write index to IR Setting disabled Write to control register or internal GRAM via WDR Read from internal GRAM and register via RDR Function
Table 7 Register Selection (Clock synchronous serial interface)
Start byte R/W 0 1 0 1 RS 0 0 1 1 Function Write index to IR Setting disabled Write to control register or internal GRAM via WDR Read from internal GRAM and register via RDR
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R61505U Table 8
IM3 IM2 IM1 IM0 System interface DB pins RAM write data 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 1 1 0 0 1 1 * 0 1 0 1 * 0 1 0 1 0 1 *
Setting disabled Setting disabled 80-system 16-bit interface 80-system 8-bit interface Clock synchronous serial interface Setting disabled Setting disabled Setting disabled Setting disabled 80-system 18-bit interface 80-system 9-bit interface Setting disabled DB17-10, DB8-1 DB17-10 Single transfer (16 bits) 2 transfers (1st: 2 bits, 2nd: 16 bits) 2 transfers (1st: 16 bits, 2nd: 2 bits) 2 transfers (1st: 8 bits, 2nd: 8 bits) 3 transfers (1st: 6 bits, 2nd: 6 bits, 3rd: 6 bits)
Instruction write transfer
Single transfer (16 bits 2 transfers (1st: 8 bits, 2nd: 8 bits) 2 transfers (1st: 8 bits, 2nd: 8 bits) Single transfer (16 bits) 2 transfers (1st: 8 bits, 2nd: 8 bits) -
(SDI, SDO) 2 transfers (1st: 8 bits, 2nd: 8 bits) DB17-0 DB17-9 Single transfer (18 bits) 2 transfers (1st: 9 bits, 2nd: 9 bits) -
2.
External Display Interface (RGB, VSYNC interfaces)
The R61505U supports RGB interface and VSYNC interface as the external interface to display moving picture. When the RGB interface is selected, the display operation is synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface operation, data (DB17-0) is written in synchronization with these signals when the polarity of enable signal (ENABLE) allows write operation in order to prevent flicker while updating display data. In VSYNC interface operation, the display operation is synchronized with the internal clock except frame synchronization, which synchronizes the display operation with the VSYNC signal. The display data is written to the internal GRAM via system interface. When writing data via VSYNC interface, there are constraints in speed and method in writing data to the internal RAM. For details, see the "VSYNC interface" section. The R61505U allows switching interface by instruction according to the display, i.e. still and/or moving picture(s) in order to transfer data only when the data is updated and thereby reduce the data transfer and power consumption for moving picture display. 3. Address Counter (AC)
The address counter (AC) gives an address to the internal GRAM. When the index of the register to set a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As the R61505U writes data to the internal GRAM, the address in the AC is automatically updated plus or minus 1. The window address function enables writing data only within the rectangular area specified in the GRAM.
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R61505U 4. Graphics RAM (GRAM)
GRAM is graphics RAM, which can store bit-pattern data of 172,800 (240RGB x 320 (dots) x 18(bits)) bytes at maximum, using 18 bits per pixel. 5. Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates liquid crystal drive voltages according to the grayscale data in the -correction registers to enable 262k-color display. For details, see the -Correction Register section. 6. Liquid crystal drive power supply circuit
The liquid crystal drive power supply circuit generates DDVDH, VGH, VGL and VCOM levels to drive liquid crystal. 7. Timing Generator
The timing generator generates a timing signal for the operation of internal circuit such as the internal GRAM. The timing signal for display operation such as RAM read operation and the timing signal for internal operation such as RAM access from the MPU are generated separately in order to avoid mutual interference. 8. Oscillator (OSC)
Internal RC oscillator generates clock signal used to operate the R61505U. The R61505U generates the RC oscillation clock using internal RC oscillator. Adjusting the frequency by external resistance is impossible. Adjust the oscillation frequency and line numbers by Frame-Frequency Adjustment Function. During the deep standby mode, RC oscillation halts to reduce power consumption. See "Oscillator" for details. 9. Liquid crystal driver Circuit
The liquid crystal driver circuit of the R61505U consists of a 720-output source driver (S1 ~ S720) and a 320-output gate driver (G1~G320). The display pattern data is latched when 720 bits of data are inputted. The latched data control the source driver and output drive waveforms. The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 720-bit source output from the source driver can be changed by setting the SS bit and the shift direction of gate output from the gate driver can be changed by setting the GS bit. The scan mode by the gate driver can be changed by setting the SM bit. Sets the gate driver pin arrangement in combination with the GS bit to select the optimal scan mode for the module. 10. Internal logic power supply regulator The internal logic power supply regulator generates internal logic power supply VDD.
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R61505U
Pin Function
Table 9 Interface
Signal IM3-1, IM0/ID I/O I Connect Function to IOGND or Select a mode to interface to an MPU. In serial interface operation, IOVCC the IM0 pin is used to set the ID bit of device code.
IM3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IM2 0 0
0 0
When not in use -
IM1 0 0
1 1
IM0/I D 0
1
Interface Mode Setting disabled Setting disabled 80-system 16-bit interface 80-system 8-bit interface Clock synchronous serial interface Setting disabled Setting disabled Setting disabled Setting disabled 80-system 18-bit interface 80-system 9-bit interface Setting disabled Setting disabled Setting disabled Setting disabled
DB Pin DB17-10, DB8-1 DB17-10 DB17-0 DB17-9 -
Colors 262,144
see Note 1
0
1
262,144
see Note 2
1 1 1 0 0 0 0 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1
*(ID) 0 1 0 1 0 1 0 1 0 1
65,536 262,144 262,144 -
Notes: 1. 65,536 colors in one transfer mode 2. 65,536 colors in two transfers mode
CS*
I
MPU
Chip select signal. Amplitude: IOVCC-IOGND Low: the R61505U is selected and accessible High: the R61505U is not selected and not accessible. Register select signal. Amplitude: IOVCC-IOGND Low: select Index or status register High: select control register Write strobe signal in 80-system bus interface operation and enables write operation when WR* is low. Synchronous clock signal (SCL) in serial interface operation. Amplitude: IOVCC-IOGND Read strobe signal in 80-system bus interface operation and enables read operation when RD* is low. Amplitude: IOVCC-IOGND
IOVCC
RS
I
MPU
IOVCC
WR*/SCL
I
MPU
IOVCC
RD* SDI
I I
MPU MPU
IOVCC
SDO
I/O
MPU
Serial data input (SDI) pin in serial interface operation. The data is IOGND or inputted on the rising edge of the SCL signal. Amplitude: IOVCCIOVCC IOGND Serial data output (SDO) pin in serial interface operation. The data is Open outputted on the falling edge of the SCL signal. Amplitude: IOVCC-IOGND
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R61505U
Signal DB0-DB17 I/O I/O Connect to MPU Function When not in use 18-bit parallel bi-directional data bus for 80-system interface operation IOGND or IOVCC (Amplitude: IOVCC-IOGND). 8-bit I/F: DB17-DB10 are used. 9-bit I/F: DB17-DB9 are used. 16-bit I/F: DB17-DB10 and DB8-1 are used. 18-bit I/F: DB17-DB0 are used. 18-bit parallel bi-directional data bus for RGB interface operation (Amplitude: IOVCC-IOGND). 6-bit I/F: DB17-DB12 are used. 16-bit I/F: DB17-DB13 and DB11-1 are used. 18-bit I/F: DB17-DB0 are used. ENABLE I MPU Data enable signal for RGB interface operation. (Amplitude: IOVCC-IOGND). Low: accessible (select) High: Not accessible (Not select) The polarity of ENABLE signal can be inverted by setting the EPL bit. VSYNC HSYNC DOTCLK FMARK I I I O MPU MPU MPU MPU Frame synchronous signal for RGB interface operation. Low active. (Amplitude: IOVCC-IOGND). Line synchronous signal for RGB interface operation. Low active. (Amplitude: IOVCC-IOGND). IOGND or IOVCC IOGND or IOVCC IOGND or IOVCC
Dot clock signal for RGB interface operation. The data input timing is IOGND or on the rising edge of DOTCLK. (Amplitude: IOVCC-IOGND). IOVCC Frame head pulse signal, which is used when writing data to the internal RAM. (Amplitude: IOVCC-IOGND). Open
Table 10 Reset, RC oscillation
Signal RESET* I/O I Connect to MPU or external RC circuit Open Function Reset signal. Initializes the R61505U when it is low. Make sure to execute a power-on reset when turning on power supply (IOVCCIOGND amplitude signal). Leave them open. When not in use -
OSC1 OSC2
I O
Open
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R61505U Table 11 Power supply
Signal VCC GND RGND VDD IOVCC I/O O Connect to Power supply Power supply Power supply Function Power supply to internal logic regulator circuit: VCC = 2.5V~3.3V. VCC IOVCC Internal logic GND: GND = 0V. Internal RAM GND. RGND must be at the same electrical potential as GND. In case of COG, connect to GND on the FPC to prevent noise. When not in use -
Stabilizing Internal logic regulator output, which is used as the power supply to capacitor internal logic. Connect a stabilizing capacitor. Power supply Power supply to the interface pins: RESET*, CS*, WR, RD*, RS, DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOVCC = 1.65V ~ 3.3V. VCC IOVCC. In case of COG, connect to VCC on the FPC if IOVCC=VCC, to prevent noise. GND for the interface pins: RESET*, CS*, WR, RD*, RS, DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. Analog GND (for logic regulator and liquid crystal power supply circuit): AGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. Power supply to the liquid crystal power supply analog circuit. Connect to an external power supply of 2.5V ~ 3.3V.
IOGND
-
Power supply Power supply Power supply
-
AGND
-
-
VCI VCILVL
I I
-
Reference VCILVL must be at the same electrical potential as VCI. power VCILVL = 2.5V ~ 3.3V. Connect to external power supply. In case of supply COG, connect to VCI on the FPC to prevent noise. Power supply or open Power supply or open Power supply or open Internal NVM power supply. Apply the following voltages on VPP1 ~ VPP2 respectively according to the power supply ON sequence. Operation mode VPP1 NVM write NVM read 9.00.1V Open VPP2 7.50.1V Open VPP3A / VPP3B GND GND
VPP1
I
Open
VPP2
I
Open
VPP3A/ VPP3B
I
GND
Rev.1.21 April 9, 2007, page 17 of 205
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R61505U Table 12 Step-up circuit
Signal VCIOUT I/O O Connect to Stabilizing capacitor, VCI1 VCIOUT Function Output voltage from the step-up circuit 1, generated from the reference voltage. The output factor is set by VC bits. Make sure to connect to stabilizing capacitor. Reference voltage of step-up circuit 1. Make sure the output voltage levels from VLOUT1, VLOUT2, VLOUT3 do not exceed the respective setting ranges. When not in use -
VCI1
I/O
-
VLOUT1
O
Stabilizing Output voltage from the step-up circuit 1, generated from VCI1. The capacitor, step-up factor is set by instruction (BT bits). Make sure to connect to DDVDH stabilizing capacitor. VLOUT1 = 4.5V ~ 6.0V VLOUT1 Power supply for the source driver liquid crystal drive unit and VCOM drive. Connect to VLOUT1. DDVDH = 4.5V ~ 6.0V
-
DDVDH VLOUT2
I O
-
Stabilizing Output voltage from the step-up circuit 2, generated from VCI1 and capacitor, DDVDH. The step-up factor is set by instruction (BT bits). Make sure VGH to connect to stabilizing capacitor. VLOUT2 = max 20.0V VLOUT2 Liquid crystal drive power supply. Connect to VLOUT2. Stabilizing Output voltage from the step-up circuit 2, generated from VCI1 and capacitor, DDVDH. The step-up factor is set by instruction (BT bits). Make sure VGL to connect to stabilizing capacitor. VLOUT3 = min -13.5V VLOUT3 Liquid crystal drive power supply. Connect to VLOUT3. Stabilizing VCOML drive power supply. Make sure to connect to stabilizing capacitor capacitor. VCL = -1.9V ~ -3.0V Step-up capacitor Step-up capacitor Capacitor connection pins for the step-up circuit 1. Capacitor connection pins for the step-up circuit 2. Connect capacitors to C23 according to the step-up factor.
VGH VLOUT3
I O
-
VGL VCL C11+, C11C12+, C12C13+, C13C21+, C21C22+, C22C23+, C23-
I O I O I O
-
Rev.1.21 April 9, 2007, page 18 of 205
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R61505U Table 13 LCD drive
Signal VREG1 OUT I/O O Connect Function to Stabilizing Output voltage generated from the reference voltage (VCILVL or capacitor VCIR). The factor is determined by instruction (VRH bits). VREG1OUT is used for (1) source driver grayscale reference voltage, (2) VCOMH level reference voltage, and (3) VCOM amplitude reference voltage. Connect to a stabilizing capacitor when in use. VREG1OUT = 4.0V ~ (DDVDH - 0.5)V VCOM O TFT panel Power supply to TFT panel's common electrode. VCOM alternates Open common between VCOMH and VCOML. The alternating cycle is set by internal electrode register. Also, the VCOM output can be started and halted by register setting. Stabilizing The High level of VCOM amplitude. The output level can be adjusted Open capacitor by either external resistor (VCOMR) or electronic volume. Make sure to connect to stabilizing capacitor. Stabilizing The Low level of VCOM amplitude. The output level can be adjusted capacitor by instruction (VDV bits). VCOML = (VCL+0.5)V ~ 0V. Make sure to connect to stabilizing capacitor. Open When not in use Open
VCOMH
O
VCOML
O
VCOMR
I
Variable Connect a variable resistor when adjusting the VCOMH level between Open resistor or VREG1OUT and GND. open GND LCD Reference level for the grayscale voltage generating circuit. Liquid crystal application voltages. To change the shift direction of segment signal output, set the SS bit as follows. When SS = 0, the data in the RAM address h00000 is outputted from S1. When SS = 1, the data in the RAM address h00000 is outputted from S720. Open
VGS S1~S720
I O
G1~G320
O
LCD
Gate line output signals. VGH: gate line select level VGL: gate line non-select level
Open
Rev.1.21 April 9, 2007, page 19 of 205
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R61505U Table 14 Others (test, dummy pins)
Signal V0T, V31T VTEST VREFC VREF VDDTEST VREFD VMON TESTA5
IOVCCDUM1-2
I/O I/O O I O I O O O O O O O O O -
Connect to Open Open AGND Open AGND Open Open Open -
Function Test pins. Leave them open. Test pin. Leave it open. Test pin. Make sure to fix to the AGND level. Test pin. Leave it open. Test pin. Make sure to fix to the AGND level. Test pin. Leave it open. Test pin. Leave it open. Test pin. Leave it open. Use them to fix the electrical potentials of unused interface pins and fixed pins. When not in use, leave it open. Test pin. Leave it open Use them to fix the electrical potentials of unused interface pins and fixed pins. When not in use, leave it open. Test pins. Leave them open. Test pins. Leave them open. Use them to fix VREFC, VDDTEST. DUMMYR1 and DUMMYR10, DUMMYR2 and DUMMYR9, DUMMYR3 and DUMMYR4, DUMMYR5 and DUMMYR8, and DUMMYR6 and DUMMYR7 are short-circuited within the chip for COG contact resistance measurement. Dummy pads. Leave them open.
When not in use Open Open Open Open Open Open Open Open Open Open Open Open Open
VCCDUM1
IOGNDDUM1-3
OSC1DUM1-4 OSC2DUM1-2 AGNDDUM1-4
DUMMYR 1-10
VGLDMY 1-4
O
-
Open
Rev.1.21 April 9, 2007, page 20 of 205
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R61505U
Signal TESTO1-38 TEST1, 2 TEST3 TEST4 TEST5 TSC TS8-0 I/O O I I I I I O Connect to IOGND IOVCC IOVCC IOGND IOGND Open Function Dummy pads. Leave them open. Test pins. Connect to IOGND. Test pin. Connect to IOVCC. Test pin. Connect to IOVCC. NVM operation enable pin. Connect to IOGND. Test pin. Connect to IOGND. Test pins. Leave them open. When not in use Open IOGND IOVCC IOVCC IOGND IOGND Open
Patents of dummy pin which is used to fix pin to VCC or GND are pending or granted. PATENT ISSUED: United States Patent No. 6,323,930 PATENT PENDING: Japanese Application No. 10-514484, Korean Application No. 19997002322 Taiwanese Application No.086103756, (PCT/JP96/02728(W098/12597)
Rev.1.21 April 9, 2007, page 21 of 205
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R61505U Pad Arrangement
Rev1.12007.04.09
Chip size: 21.56mmx 1.28mm Chip thickness: 280/400m(typ.) Pad coordinates: Pad center Coordinates origin: Chip center

PAD No.
1-a
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298

No.1
Au BUMP size: 50.00 mx 80.00m No.1 - 298
21.00mx100.00m No.299 - 1354
Au BUMP pitch: See PAD coordinates table AuBUMP height: 15m(typ.) No. in the Figure corresponds to No. in PAD coordinates table.
Alignment Mark (1-a)(1-b)
100 50 30
30
40
30
TopView
BUMP
Chip
No.298
DUMMYR1 DUMMYR2 TESTO1 VCCDUM VPP1 VPP1 VPP1 VPP2 VPP2 VPP2 VPP2 VPP2 VPP3A VPP3A VPP3B TESTO2 IOGNDDUM TESTO3 TEST1 TEST2 TEST4 TEST5 TEST3 IM0/ID IM1 IM2 IM3 TESTO4 IOVCCDUM1 TESTO5 RESET* VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 TESTO6 IOGNDDUM2 TESTO7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI RD* WR*/SCL RS CS* TESTO8 IOVCCDUM2 TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 TSC TESTO10 IOGNDDUM3 TESTO11 TESTO12 OSC1DUM1 OSC1DUM2 OSC1 OSC1DUM3 OSC1DUM4 OSC2 OSC2DUM1 OSC2DUM2 DUMMYR3 DUMMYR4 IOGND IOGND IOGND IOGND IOGND IOGND IOGND IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD TESTO13 VREFD TESTO14 VREF TESTO15 VREFC TESTO16 VDDTEST AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND RGND RGND RGND RGND RGND RGND RGND RGND RGND RGND TESTO17 VTEST TESTO18 VGS TESTO19 V0T TESTO20 VMON TESTO21 V31T VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO22 TESTO23 VREG1OUT TESTO24 TESTA5 TESTO25 VCOMR TESTO26 VCL VCL VCL VLOUT1 VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C12C12C12C12C12C12+ C12+ C12+ C12+ C12+ C11C11C11C11C11C11+ C11+ C11+ C11+ C11+ AGNDDUM1 VLOUT3 VLOUT3 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM2 AGNDDUM3 AGNDDUM4 VLOUT2 VLOUT2 VGH VGH VGH VGH TESTO27 C13C13C13TESTO28 C13+ C13+ C13+ TESTO29 C21C21C21C21+ C21+ C21+ C22C22C22C22+ C22+ C22+ C23C23C23C23+ C23+ C23+ TESTO30 DUMMYR5 DUMMYR6
220um 60um
DUMMYR1DUMMYR10: Short-circuited DUMMYR2DUMMYR9: Short-circuited

TESTO38 TESTO37 DUMMYR10 DUMMYR9 VGLDMY4 G2 G4 G6 G8 G10

30
G312 G314 G316 G318 G320 VGLDMY3 TESTO36 TESTO35 S1 S2 S3 S4 S5 S6 S7 S8
100
50
40

R61505U Staggered output Top View (Bump View)

S716 S717 S718 S719 S720 TESTO34

TESTO33 VGLDMY2 G319 G317 G315 G313 G311

DUMMYR5DUMMYR8: Short-circuited DUMMYR6DUMMYR7: Short-circuited
1-b

G9 G7 G5 G3 G1 VGLDMY1 DUMMYR8 DUMMYR7 TESTO32 TESTO31
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R61505U
Chip size: 21.56 mm x 1.28 mm Chip thickness: 280/400m (typ.) PAD coordinates: PAD center PAD coordinates origin: Chip center Au bump size (1) 50m 80m I/O output side: No. 1 - No. 298 (2) 21m 100m Liquid crystal output side: No. 299 - No. 1354 Au bump pitch: See PAD coordinates table Au bump height: 15m(typ.) No. in the Figure corresponds to No. in the PAD coordinates table Alignment mark Alignment mark shape
Type A
g a b c d e f h
Non-pattern area
X -10613.0 10613.0 Y -468.0 -468.0
Unit (m) e: 40 a: 30 f: 30 b: 40 g: 100 c: 30 h: 100 d: 30
Type A
Rev.1.21 April 9, 2007, page 23 of 205
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R61505U Pad Coordinate Unitm
pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pad name DUMMYR1 DUMMYR2 TESTO1 VCCDUM1 VPP1 VPP1 VPP1 VPP2 VPP2 VPP2 VPP2 VPP2 VPP3A VPP3A VPP3B TESTO2 IOGNDDUM1 TESTO3 TEST1 TEST2 TEST4 TEST5 TEST3 IM0/ID IM1 IM2 IM3 TESTO4 IOVCCDUM1 TESTO5 RESET* VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 TESTO6 IOGNDDUM2 TESTO7 DB7 DB6 X -10395.0 -10325.0 -10255.0 -10185.0 -10115.0 -10045.0 -9975.0 -9905.0 -9835.0 -9765.0 -9695.0 -9625.0 -9555.0 -9485.0 -9415.0 -9345.0 -9275.0 -9205.0 -9135.0 -9065.0 -8995.0 -8925.0 -8855.0 -8785.0 -8715.0 -8645.0 -8575.0 -8505.0 -8435.0 -8365.0 -8295.0 -8225.0 -8155.0 -8085.0 -8015.0 -7945.0 -7875.0 -7805.0 -7735.0 -7665.0 -7595.0 -7525.0 -7455.0 -7385.0 -7315.0 -7245.0 -7175.0 -7105.0 -7035.0 -6965.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 pad No 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pad name DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI RD* WR*/SCL RS CS* TESTO8 IOVCCDUM2 TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 TSC TESTO10 IOGNDDUM3 TESTO11 TESTO12 OSC1DUM1 OSC1DUM2 OSC1 OSC1DUM3 OSC1DUM4 OSC2 OSC2DUM1 OSC2DUM2 DUMMYR3 DUMMYR4 IOGND IOGND IOGND IOGND IOGND IOGND IOGND IOVCC IOVCC IOVCC
2007/04/09 rev1.21 X -6895.0 -6825.0 -6755.0 -6685.0 -6615.0 -6545.0 -6475.0 -6405.0 -6335.0 -6265.0 -6195.0 -6125.0 -6055.0 -5985.0 -5915.0 -5845.0 -5775.0 -5705.0 -5635.0 -5565.0 -5495.0 -5425.0 -5355.0 -5285.0 -5215.0 -5145.0 -5075.0 -5005.0 -4935.0 -4865.0 -4795.0 -4725.0 -4655.0 -4585.0 -4515.0 -4445.0 -4375.0 -4305.0 -4235.0 -4165.0 -4095.0 -4025.0 -3955.0 -3885.0 -3815.0 -3745.0 -3675.0 -3605.0 -3535.0 -3465.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5
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R61505U Pad Coordinate Unitm
pad No 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 pad name IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC VDDOUT VDDOUT VDDOUT VDDOUT VDD VDD VDD VDD VDD VDD VDD VDD VDD TESTO13 VREFD TESTO14 VREF TESTO15 VREFC TESTO16 VDDTEST AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND X -3395.0 -3325.0 -3255.0 -3185.0 -3115.0 -3045.0 -2975.0 -2905.0 -2835.0 -2765.0 -2695.0 -2625.0 -2555.0 -2485.0 -2415.0 -2345.0 -2275.0 -2205.0 -2135.0 -2065.0 -1995.0 -1925.0 -1855.0 -1785.0 -1715.0 -1645.0 -1575.0 -1505.0 -1435.0 -1365.0 -1295.0 -1225.0 -1155.0 -1085.0 -1015.0 -945.0 -875.0 -805.0 -735.0 -665.0 -595.0 -525.0 -455.0 -385.0 -315.0 -245.0 -175.0 -105.0 -35.0 35.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 pad No 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 pad name RGND RGND RGND RGND RGND RGND RGND RGND RGND RGND TESTO17 VTEST TESTO18 VGS TESTO19 V0T TESTO20 VMON TESTO21 V31T VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO22 TESTO23 VREG1OUT TESTO24 TESTA5 TESTO25 VCOMR TESTO26 VCL VCL VCL VLOUT1
2007/04/09 rev1.21 X 105.0 175.0 245.0 315.0 385.0 455.0 525.0 595.0 665.0 735.0 805.0 875.0 945.0 1015.0 1085.0 1155.0 1225.0 1295.0 1365.0 1435.0 1505.0 1575.0 1645.0 1715.0 1785.0 1855.0 1925.0 1995.0 2065.0 2135.0 2205.0 2275.0 2345.0 2415.0 2485.0 2555.0 2625.0 2695.0 2765.0 2835.0 2905.0 2975.0 3045.0 3115.0 3185.0 3255.0 3325.0 3395.0 3465.0 3535.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5
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R61505U Pad Coordinate Unitm
pad No 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 pad name VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C12C12C12C12C12C12+ C12+ C12+ C12+ C12+ C11C11C11C11C11C11+ C11+ C11+ C11+ C11+ AGNDDUM1 VLOUT3 VLOUT3 VGL X 3605.0 3675.0 3745.0 3815.0 3885.0 3955.0 4025.0 4095.0 4165.0 4235.0 4305.0 4375.0 4445.0 4515.0 4585.0 4655.0 4725.0 4795.0 4865.0 4935.0 5005.0 5075.0 5145.0 5215.0 5285.0 5355.0 5425.0 5495.0 5565.0 5635.0 5705.0 5775.0 5845.0 5915.0 5985.0 6055.0 6125.0 6195.0 6265.0 6335.0 6405.0 6475.0 6545.0 6615.0 6685.0 6755.0 6825.0 6895.0 6965.0 7035.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 pad No 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 pad name VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM2 AGNDDUM3 AGNDDUM4 VLOUT2 VLOUT2 VGH VGH VGH VGH TESTO27 C13C13C13TESTO28 C13+ C13+ C13+ TESTO29 C21C21C21C21+ C21+ C21+ C22C22C22C22+ C22+ C22+ C23C23C23C23+ C23+ C23+ TESTO30 DUMMYR5 DUMMYR6 TESTO31 TESTO32
2007/04/09 rev1.21 X 7105.0 7175.0 7245.0 7315.0 7385.0 7455.0 7525.0 7595.0 7665.0 7735.0 7805.0 7875.0 7945.0 8015.0 8085.0 8155.0 8225.0 8295.0 8365.0 8435.0 8505.0 8575.0 8645.0 8715.0 8785.0 8855.0 8925.0 8995.0 9065.0 9135.0 9205.0 9275.0 9345.0 9415.0 9485.0 9555.0 9625.0 9695.0 9765.0 9835.0 9905.0 9975.0 10045.0 10115.0 10185.0 10255.0 10325.0 10395.0 10670.0 10650.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 511.5 386.5
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R61505U Pad Coordinate Unitm
pad No 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 pad name DUMMYR7 DUMMYR8 VGLDMY1 G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 X 10630.0 10610.0 10590.0 10570.0 10550.0 10530.0 10510.0 10490.0 10470.0 10450.0 10430.0 10410.0 10390.0 10370.0 10350.0 10330.0 10310.0 10290.0 10270.0 10250.0 10230.0 10210.0 10190.0 10170.0 10150.0 10130.0 10110.0 10090.0 10070.0 10050.0 10030.0 10010.0 9990.0 9970.0 9950.0 9930.0 9910.0 9890.0 9870.0 9850.0 9830.0 9810.0 9790.0 9770.0 9750.0 9730.0 9710.0 9690.0 9670.0 9650.0 Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 pad No 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 pad name G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 G133 G135 G137 G139 G141 G143 G145 G147 G149 G151 G153 G155 G157 G159 G161 G163 G165 G167 G169 G171 G173 G175 G177 G179 G181 G183 G185 G187 G189 G191 G193
2007/04/09 rev1.21 X 9630.0 9610.0 9590.0 9570.0 9550.0 9530.0 9510.0 9490.0 9470.0 9450.0 9430.0 9410.0 9390.0 9370.0 9350.0 9330.0 9310.0 9290.0 9270.0 9250.0 9230.0 9210.0 9190.0 9170.0 9150.0 9130.0 9110.0 9090.0 9070.0 9050.0 9030.0 9010.0 8990.0 8970.0 8950.0 8930.0 8910.0 8890.0 8870.0 8850.0 8830.0 8810.0 8790.0 8770.0 8750.0 8730.0 8710.0 8690.0 8670.0 8650.0 Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
www.DataSheet.in
R61505U Pad Coordinate Unitm
pad No 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 pad name G195 G197 G199 G201 G203 G205 G207 G209 G211 G213 G215 G217 G219 G221 G223 G225 G227 G229 G231 G233 G235 G237 G239 G241 G243 G245 G247 G249 G251 G253 G255 G257 G259 G261 G263 G265 G267 G269 G271 G273 G275 G277 G279 G281 G283 G285 G287 G289 G291 G293 X 8630.0 8610.0 8590.0 8570.0 8550.0 8530.0 8510.0 8490.0 8470.0 8450.0 8430.0 8410.0 8390.0 8370.0 8350.0 8330.0 8310.0 8290.0 8270.0 8250.0 8230.0 8210.0 8190.0 8170.0 8150.0 8130.0 8110.0 8090.0 8070.0 8050.0 8030.0 8010.0 7990.0 7970.0 7950.0 7930.0 7910.0 7890.0 7870.0 7850.0 7830.0 7810.0 7790.0 7770.0 7750.0 7730.0 7710.0 7690.0 7670.0 7650.0 Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 pad No 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 pad name G295 G297 G299 G301 G303 G305 G307 G309 G311 G313 G315 G317 G319 VGLDMY2 TESTO33 TESTO34 S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 S709 S708 S707 S706 S705 S704 S703 S702 S701 S700 S699 S698 S697 S696 S695 S694 S693 S692 S691 S690 S689 S688 S687
2007/04/09 rev1.21 X 7630.0 7610.0 7590.0 7570.0 7550.0 7530.0 7510.0 7490.0 7470.0 7450.0 7430.0 7410.0 7390.0 7370.0 7350.0 7130.0 7110.0 7090.0 7070.0 7050.0 7030.0 7010.0 6990.0 6970.0 6950.0 6930.0 6910.0 6890.0 6870.0 6850.0 6830.0 6810.0 6790.0 6770.0 6750.0 6730.0 6710.0 6690.0 6670.0 6650.0 6630.0 6610.0 6590.0 6570.0 6550.0 6530.0 6510.0 6490.0 6470.0 6450.0 Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
www.DataSheet.in
R61505U Pad Coordinate Unitm
pad No 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 pad name S686 S685 S684 S683 S682 S681 S680 S679 S678 S677 S676 S675 S674 S673 S672 S671 S670 S669 S668 S667 S666 S665 S664 S663 S662 S661 S660 S659 S658 S657 S656 S655 S654 S653 S652 S651 S650 S649 S648 S647 S646 S645 S644 S643 S642 S641 S640 S639 S638 S637 X 6430.0 6410.0 6390.0 6370.0 6350.0 6330.0 6310.0 6290.0 6270.0 6250.0 6230.0 6210.0 6190.0 6170.0 6150.0 6130.0 6110.0 6090.0 6070.0 6050.0 6030.0 6010.0 5990.0 5970.0 5950.0 5930.0 5910.0 5890.0 5870.0 5850.0 5830.0 5810.0 5790.0 5770.0 5750.0 5730.0 5710.0 5690.0 5670.0 5650.0 5630.0 5610.0 5590.0 5570.0 5550.0 5530.0 5510.0 5490.0 5470.0 5450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 pad No 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 pad name S636 S635 S634 S633 S632 S631 S630 S629 S628 S627 S626 S625 S624 S623 S622 S621 S620 S619 S618 S617 S616 S615 S614 S613 S612 S611 S610 S609 S608 S607 S606 S605 S604 S603 S602 S601 S600 S599 S598 S597 S596 S595 S594 S593 S592 S591 S590 S589 S588 S587
2007/04/09 rev1.21 X 5430.0 5410.0 5390.0 5370.0 5350.0 5330.0 5310.0 5290.0 5270.0 5250.0 5230.0 5210.0 5190.0 5170.0 5150.0 5130.0 5110.0 5090.0 5070.0 5050.0 5030.0 5010.0 4990.0 4970.0 4950.0 4930.0 4910.0 4890.0 4870.0 4850.0 4830.0 4810.0 4790.0 4770.0 4750.0 4730.0 4710.0 4690.0 4670.0 4650.0 4630.0 4610.0 4590.0 4570.0 4550.0 4530.0 4510.0 4490.0 4470.0 4450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
www.DataSheet.in
R61505U Pad Coordinate Unitm
pad No 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 pad name S586 S585 S584 S583 S582 S581 S580 S579 S578 S577 S576 S575 S574 S573 S572 S571 S570 S569 S568 S567 S566 S565 S564 S563 S562 S561 S560 S559 S558 S557 S556 S555 S554 S553 S552 S551 S550 S549 S548 S547 S546 S545 S544 S543 S542 S541 S540 S539 S538 S537 X 4430.0 4410.0 4390.0 4370.0 4350.0 4330.0 4310.0 4290.0 4270.0 4250.0 4230.0 4210.0 4190.0 4170.0 4150.0 4130.0 4110.0 4090.0 4070.0 4050.0 4030.0 4010.0 3990.0 3970.0 3950.0 3930.0 3910.0 3890.0 3870.0 3850.0 3830.0 3810.0 3790.0 3770.0 3750.0 3730.0 3710.0 3690.0 3670.0 3650.0 3630.0 3610.0 3590.0 3570.0 3550.0 3530.0 3510.0 3490.0 3470.0 3450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 pad No 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 pad name S536 S535 S534 S533 S532 S531 S530 S529 S528 S527 S526 S525 S524 S523 S522 S521 S520 S519 S518 S517 S516 S515 S514 S513 S512 S511 S510 S509 S508 S507 S506 S505 S504 S503 S502 S501 S500 S499 S498 S497 S496 S495 S494 S493 S492 S491 S490 S489 S488 S487
2007/04/09 rev1.21 X 3430.0 3410.0 3390.0 3370.0 3350.0 3330.0 3310.0 3290.0 3270.0 3250.0 3230.0 3210.0 3190.0 3170.0 3150.0 3130.0 3110.0 3090.0 3070.0 3050.0 3030.0 3010.0 2990.0 2970.0 2950.0 2930.0 2910.0 2890.0 2870.0 2850.0 2830.0 2810.0 2790.0 2770.0 2750.0 2730.0 2710.0 2690.0 2670.0 2650.0 2630.0 2610.0 2590.0 2570.0 2550.0 2530.0 2510.0 2490.0 2470.0 2450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
www.DataSheet.in
R61505U Pad Coordinate Unitm
pad No 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 pad name S486 S485 S484 S483 S482 S481 S480 S479 S478 S477 S476 S475 S474 S473 S472 S471 S470 S469 S468 S467 S466 S465 S464 S463 S462 S461 S460 S459 S458 S457 S456 S455 S454 S453 S452 S451 S450 S449 S448 S447 S446 S445 S444 S443 S442 S441 S440 S439 S438 S437 X 2430.0 2410.0 2390.0 2370.0 2350.0 2330.0 2310.0 2290.0 2270.0 2250.0 2230.0 2210.0 2190.0 2170.0 2150.0 2130.0 2110.0 2090.0 2070.0 2050.0 2030.0 2010.0 1990.0 1970.0 1950.0 1930.0 1910.0 1890.0 1870.0 1850.0 1830.0 1810.0 1790.0 1770.0 1750.0 1730.0 1710.0 1690.0 1670.0 1650.0 1630.0 1610.0 1590.0 1570.0 1550.0 1530.0 1510.0 1490.0 1470.0 1450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 pad No 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 pad name S436 S435 S434 S433 S432 S431 S430 S429 S428 S427 S426 S425 S424 S423 S422 S421 S420 S419 S418 S417 S416 S415 S414 S413 S412 S411 S410 S409 S408 S407 S406 S405 S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387
2007/04/09 rev1.21 X 1430.0 1410.0 1390.0 1370.0 1350.0 1330.0 1310.0 1290.0 1270.0 1250.0 1230.0 1210.0 1190.0 1170.0 1150.0 1130.0 1110.0 1090.0 1070.0 1050.0 1030.0 1010.0 990.0 970.0 950.0 930.0 910.0 890.0 870.0 850.0 830.0 810.0 790.0 770.0 750.0 730.0 710.0 690.0 670.0 650.0 630.0 610.0 590.0 570.0 550.0 530.0 510.0 490.0 470.0 450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
www.DataSheet.in
R61505U Pad Coordinate Unitm
pad No 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 pad name S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 X 430.0 410.0 390.0 370.0 350.0 330.0 310.0 290.0 270.0 250.0 230.0 210.0 190.0 170.0 150.0 130.0 110.0 90.0 70.0 50.0 30.0 10.0 -10.0 -30.0 -50.0 -70.0 -90.0 -110.0 -130.0 -150.0 -170.0 -190.0 -210.0 -230.0 -250.0 -270.0 -290.0 -310.0 -330.0 -350.0 -370.0 -390.0 -410.0 -430.0 -450.0 -470.0 -490.0 -510.0 -530.0 -550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 pad No 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 pad name S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287
2007/04/09 rev1.21 X -570.0 -590.0 -610.0 -630.0 -650.0 -670.0 -690.0 -710.0 -730.0 -750.0 -770.0 -790.0 -810.0 -830.0 -850.0 -870.0 -890.0 -910.0 -930.0 -950.0 -970.0 -990.0 -1010.0 -1030.0 -1050.0 -1070.0 -1090.0 -1110.0 -1130.0 -1150.0 -1170.0 -1190.0 -1210.0 -1230.0 -1250.0 -1270.0 -1290.0 -1310.0 -1330.0 -1350.0 -1370.0 -1390.0 -1410.0 -1430.0 -1450.0 -1470.0 -1490.0 -1510.0 -1530.0 -1550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
www.DataSheet.in
R61505U Pad Coordinate Unitm
pad No 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 pad name S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 X -1570.0 -1590.0 -1610.0 -1630.0 -1650.0 -1670.0 -1690.0 -1710.0 -1730.0 -1750.0 -1770.0 -1790.0 -1810.0 -1830.0 -1850.0 -1870.0 -1890.0 -1910.0 -1930.0 -1950.0 -1970.0 -1990.0 -2010.0 -2030.0 -2050.0 -2070.0 -2090.0 -2110.0 -2130.0 -2150.0 -2170.0 -2190.0 -2210.0 -2230.0 -2250.0 -2270.0 -2290.0 -2310.0 -2330.0 -2350.0 -2370.0 -2390.0 -2410.0 -2430.0 -2450.0 -2470.0 -2490.0 -2510.0 -2530.0 -2550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 pad No 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 pad name S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187
2007/04/09 rev1.21 X -2570.0 -2590.0 -2610.0 -2630.0 -2650.0 -2670.0 -2690.0 -2710.0 -2730.0 -2750.0 -2770.0 -2790.0 -2810.0 -2830.0 -2850.0 -2870.0 -2890.0 -2910.0 -2930.0 -2950.0 -2970.0 -2990.0 -3010.0 -3030.0 -3050.0 -3070.0 -3090.0 -3110.0 -3130.0 -3150.0 -3170.0 -3190.0 -3210.0 -3230.0 -3250.0 -3270.0 -3290.0 -3310.0 -3330.0 -3350.0 -3370.0 -3390.0 -3410.0 -3430.0 -3450.0 -3470.0 -3490.0 -3510.0 -3530.0 -3550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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R61505U Pad Coordinate Unitm
pad No 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 pad name S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 X -3570.0 -3590.0 -3610.0 -3630.0 -3650.0 -3670.0 -3690.0 -3710.0 -3730.0 -3750.0 -3770.0 -3790.0 -3810.0 -3830.0 -3850.0 -3870.0 -3890.0 -3910.0 -3930.0 -3950.0 -3970.0 -3990.0 -4010.0 -4030.0 -4050.0 -4070.0 -4090.0 -4110.0 -4130.0 -4150.0 -4170.0 -4190.0 -4210.0 -4230.0 -4250.0 -4270.0 -4290.0 -4310.0 -4330.0 -4350.0 -4370.0 -4390.0 -4410.0 -4430.0 -4450.0 -4470.0 -4490.0 -4510.0 -4530.0 -4550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 pad No 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 pad name S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87
2007/04/09 rev1.21 X -4570.0 -4590.0 -4610.0 -4630.0 -4650.0 -4670.0 -4690.0 -4710.0 -4730.0 -4750.0 -4770.0 -4790.0 -4810.0 -4830.0 -4850.0 -4870.0 -4890.0 -4910.0 -4930.0 -4950.0 -4970.0 -4990.0 -5010.0 -5030.0 -5050.0 -5070.0 -5090.0 -5110.0 -5130.0 -5150.0 -5170.0 -5190.0 -5210.0 -5230.0 -5250.0 -5270.0 -5290.0 -5310.0 -5330.0 -5350.0 -5370.0 -5390.0 -5410.0 -5430.0 -5450.0 -5470.0 -5490.0 -5510.0 -5530.0 -5550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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R61505U Pad Coordinate Unitm
pad No 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 pad name S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 X -5570.0 -5590.0 -5610.0 -5630.0 -5650.0 -5670.0 -5690.0 -5710.0 -5730.0 -5750.0 -5770.0 -5790.0 -5810.0 -5830.0 -5850.0 -5870.0 -5890.0 -5910.0 -5930.0 -5950.0 -5970.0 -5990.0 -6010.0 -6030.0 -6050.0 -6070.0 -6090.0 -6110.0 -6130.0 -6150.0 -6170.0 -6190.0 -6210.0 -6230.0 -6250.0 -6270.0 -6290.0 -6310.0 -6330.0 -6350.0 -6370.0 -6390.0 -6410.0 -6430.0 -6450.0 -6470.0 -6490.0 -6510.0 -6530.0 -6550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 pad No 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 pad name S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 TESTO35 TESTO36 VGLDMY3 G320 G318 G316 G314 G312 G310 G308 G306 G304 G302 G300
2007/04/09 rev1.21 X -6570.0 -6590.0 -6610.0 -6630.0 -6650.0 -6670.0 -6690.0 -6710.0 -6730.0 -6750.0 -6770.0 -6790.0 -6810.0 -6830.0 -6850.0 -6870.0 -6890.0 -6910.0 -6930.0 -6950.0 -6970.0 -6990.0 -7010.0 -7030.0 -7050.0 -7070.0 -7090.0 -7110.0 -7130.0 -7150.0 -7170.0 -7190.0 -7210.0 -7230.0 -7250.0 -7270.0 -7290.0 -7350.0 -7370.0 -7390.0 -7410.0 -7430.0 -7450.0 -7470.0 -7490.0 -7510.0 -7530.0 -7550.0 -7570.0 -7590.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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R61505U Pad Coordinate Unitm
pad No 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 pad name G298 G296 G294 G292 G290 G288 G286 G284 G282 G280 G278 G276 G274 G272 G270 G268 G266 G264 G262 G260 G258 G256 G254 G252 G250 G248 G246 G244 G242 G240 G238 G236 G234 G232 G230 G228 G226 G224 G222 G220 G218 G216 G214 G212 G210 G208 G206 G204 G202 G200 X -7610.0 -7630.0 -7650.0 -7670.0 -7690.0 -7710.0 -7730.0 -7750.0 -7770.0 -7790.0 -7810.0 -7830.0 -7850.0 -7870.0 -7890.0 -7910.0 -7930.0 -7950.0 -7970.0 -7990.0 -8010.0 -8030.0 -8050.0 -8070.0 -8090.0 -8110.0 -8130.0 -8150.0 -8170.0 -8190.0 -8210.0 -8230.0 -8250.0 -8270.0 -8290.0 -8310.0 -8330.0 -8350.0 -8370.0 -8390.0 -8410.0 -8430.0 -8450.0 -8470.0 -8490.0 -8510.0 -8530.0 -8550.0 -8570.0 -8590.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 pad No 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 pad name G198 G196 G194 G192 G190 G188 G186 G184 G182 G180 G178 G176 G174 G172 G170 G168 G166 G164 G162 G160 G158 G156 G154 G152 G150 G148 G146 G144 G142 G140 G138 G136 G134 G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100
2007/04/09 rev1.21 X -8610.0 -8630.0 -8650.0 -8670.0 -8690.0 -8710.0 -8730.0 -8750.0 -8770.0 -8790.0 -8810.0 -8830.0 -8850.0 -8870.0 -8890.0 -8910.0 -8930.0 -8950.0 -8970.0 -8990.0 -9010.0 -9030.0 -9050.0 -9070.0 -9090.0 -9110.0 -9130.0 -9150.0 -9170.0 -9190.0 -9210.0 -9230.0 -9250.0 -9270.0 -9290.0 -9310.0 -9330.0 -9350.0 -9370.0 -9390.0 -9410.0 -9430.0 -9450.0 -9470.0 -9490.0 -9510.0 -9530.0 -9550.0 -9570.0 -9590.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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R61505U Pad Coordinate Unitm
pad No 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 pad name G98 G96 G94 G92 G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 VGLDMY4 X -9610.0 -9630.0 -9650.0 -9670.0 -9690.0 -9710.0 -9730.0 -9750.0 -9770.0 -9790.0 -9810.0 -9830.0 -9850.0 -9870.0 -9890.0 -9910.0 -9930.0 -9950.0 -9970.0 -9990.0 -10010.0 -10030.0 -10050.0 -10070.0 -10090.0 -10110.0 -10130.0 -10150.0 -10170.0 -10190.0 -10210.0 -10230.0 -10250.0 -10270.0 -10290.0 -10310.0 -10330.0 -10350.0 -10370.0 -10390.0 -10410.0 -10430.0 -10450.0 -10470.0 -10490.0 -10510.0 -10530.0 -10550.0 -10570.0 -10590.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 pad No 1351 1352 1353 1354 pad name DUMMYR9 DUMMYR10 TESTO37 TESTO38
2007/04/09 rev1.21 X -10610.0 -10630.0 -10650.0 -10670.0 Y 386.5 511.5 386.5 511.5
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R61505U Pad Coordinate Unitm
Alignment mark 1-a 1-b X -10613.0 10613.0 Y -468.0 -468.0
2007/04/09 rev1.21
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R61505U
BUMP arrangement
20 21
100
S1 ~ S720, G1 ~ G320 DUMMY* DUMMYR* TESTO* VGLDMY* (No.299 ~ No.1354)
225
25
S = 2100 m2
Unit: m
50
I/O pins (No.1 ~ No.298)
20 80
S = 4000 m2
Min. 70
Unit: m
Figure 2
Rev.1.21 April 9, 2007, page 39 of 205
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R61505U Recommended Connection Example and Resistance
Rev1.22007.04.09

PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298
1-a

open open open open VPP1 25ohm
VPP2
15ohm
VPP3
25ohm open open
IOVCC IM0/ID IM1 IM2 IM3
100ohm
100ohm 100ohm 100ohm 100ohm
open open RESET* VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm
open open open DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI RD* WR*/SCL RS CS*
100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm 100ohm
open open open FMARK
100ohm
open open open open open open open open open open open open open open open open open open open open open open
10ohm
IOVCC
10ohm
VCC
10ohm
5ohm
open open
open
open open open
5ohm
15ohm GND
5ohm
open open open VGS
100ohm
open open open open open open 10ohm
10ohm
10ohm
open open open open open open
25ohm
10ohm
10ohm
100ohm
VCI 5ohm
15ohm
15ohm
15ohm
15ohm open
10ohm
open open open
20ohm
open
25ohm open 25ohm open
25ohm 25ohm
25ohm 25ohm
25ohm 25ohm open open open
DUMMYR1 DUMMYR2 TESTO1 VCCDUM VPP1 VPP1 VPP1 VPP2 VPP2 VPP2 VPP2 VPP2 VPP3A VPP3A VPP3B TESTO2 IOGNDDUM TESTO3 TEST1 TEST2 TEST4 TEST5 TEST3 IM0/ID IM1 IM2 IM3 TESTO4 IOVCCDUM1 TESTO5 RESET* VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 TESTO6 IOGNDDUM2 TESTO7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI RD* WR*/SCL RS CS* TESTO8 IOVCCDUM2 TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 TSC TESTO10 IOGNDDUM3 TESTO11 TESTO12 OSC1DUM1 OSC1DUM2 OSC1 OSC1DUM3 OSC1DUM4 OSC2 OSC2DUM1 OSC2DUM2 DUMMYR3 DUMMYR4 IOGND IOGND IOGND IOGND IOGND IOGND IOGND IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD TESTO13 VREFD TESTO14 VREF TESTO15 VREFC TESTO16 VDDTEST AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND RGND RGND RGND RGND RGND RGND RGND RGND RGND RGND TESTO17 VTEST TESTO18 VGS TESTO19 V0T TESTO20 VMON TESTO21 V31T VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO22 TESTO23 VREG1OUT TESTO24 TESTA5 TESTO25 VcomR TESTO26 VCL VCL VCL VLOUT1 VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C12- C12- C12- C12- C12- C12+ C12+ C12+ C12+ C12+ C11- C11- C11- C11- C11- C11+ C11+ C11+ C11+ C11+ AGNDDUM1 VLOUT3 VLOUT3 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM2 AGNDDUM3 AGNDDUM4 VLOUT2 VLOUT2 VGH VGH VGH VGH TESTO27 C13- C13- C13- TESTO28 C13+ C13+ C13+ TESTO29 C21- C21- C21- C21+ C21+ C21+ C22- C22- C22- C22+ C22+ C22+ C23- C23- C23- C23+ C23+ C23+ TESTO30 DUMMYR5 DUMMYR6
No.1
TESTO38 TESTO37 DUMMYR10 DUMMYR9 VGLDMY4 G2 G4 G6 G8 G10
60um
G312 G314 G316 G318 G320 VGLDMY3 TESTO36 TESTO35 S1 S2 S3 S4 S5 S6 S7 S8
R61505U Staggered output Top View (Bump View)

S716 S717 S718 S719 S720 TESTO34
220um

TESTO33 VGLDMY2 G319 G317 G315 G313 G311

No.298
1-b

G9 G7 G5 G3 G1 VGLDMY1 DUMMYR8 DUMMYR7 TESTO32 TESTO31
Glass substrate
Note: The wiring resistance is recommended values. It is desireble to set the resistance as small as possible.
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R61505U
GRAM address map
Table 15 GRAM address and display position on the panel (SS = 0, BGR = 0)
S709 S710 S711 S712 S713 S714 S715 S716 S717 S718 S719 : h130EF h131EF h132EF h133EF h134EF h135EF h136EF h137EF h138EF h139EF h13AEF h13BEF h13CEF h13DEF h13EEF h13FEF S10 S11 S12 S1 S2 S3 S4 S5 S6 S7 S8 S9 S/G pin GS=0 GS=1 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 : G305 G306 G307 G308 G309 G310 G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 G310 G309 G308 G307 G306 G305 G304 G303 G302 G301 : G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 ...... ..... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... : ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... S720
WD[17:0] h00000 h00100 h00200 h00300 h00400 h00500 h00600 h00700 h00800 h00900 h00A00 h00B00 h00C00 h00D00 h00E00 h00F00 h01000 h01100 h01200 h01300 : h13000 h13100 h13200 h13300 h13400 h13500 h13600 h13700 h13800 h13900 h13A00 h13B00 h13C00 h13D00 h13E00 h13F00
WD[17:0] h00001 h00101 h00201 h00301 h00401 h00501 h00601 h00701 h00801 h00901 h00A01 h00B01 h00C01 h00D01 h00E01 h00F01 h01001 h01101 h01201 h01301 : h13001 h13101 h13201 h13301 h13401 h13501 h13601 h13701 h13801 h13901 h13A01 h13B01 h13C01 h13D01 h13E01 h13F01
WD[17:0] h00002 h00102 h00202 h00302 h00402 h00502 h00602 h00702 h00802 h00902 h00A02 h00B02 h00C02 h00D02 h00E02 h00F02 h01002 h01102 h01202 h01302 : h13002 h13102 h13202 h13302 h13402 h13502 h13602 h13702 h13802 h13902 h13A02 h13B02 h13C02 h13D02 h13E02 h13F02
WD[17:0] h00003 h00103 h00203 h00303 h00403 h00503 h00603 h00703 h00803 h00903 h00A03 h00B03 h00C03 h00D03 h00E03 h00F03 h01003 h01103 h01203 h01303 : h13003 h13103 h13203 h13303 h13403 h13503 h13603 h13703 h13803 h13903 h13A03 h13B03 h13C03 h13D03 h13E03 h13F03
WD[17:0] h000EC h001EC h002EC h003EC h004EC h005EC h006EC h007EC h008EC h009EC h00AEC h00BEC h00CEC h00DEC h00EEC h00FEC h010EC h011EC h012EC h013EC : h130EC h131EC h132EC h133EC h134EC h135EC h136EC h137EC h138EC h139EC h13AEC h13BEC h13CEC h13DEC h13EEC h13FEC
WD[17:0] h000ED h001ED h002ED h003ED h004ED h005ED h006ED h007ED h008ED h009ED h00AED h00BED h00CED h00DED h00EED h00FED h010ED h011ED h012ED h013ED : h130ED h131ED h132ED h133ED h134ED h135ED h136ED h137ED h138ED h139ED h13AED h13BED h13CED h13DED h13EED h13FED
WD[17:0] h000EE h001EE h002EE h003EE h004EE h005EE h006EE h007EE h008EE h009EE h00AEE h00BEE h00CEE h00DEE h00EEE h00FEE h010EE h011EE h012EE h013EE : h130EE h131EE h132EE h133EE h134EE h135EE h136EE h137EE h138EE h139EE h13AEE h13BEE h13CEE h13DEE h13EEE h13FEE
WD[17:0] h000EF h001EF h002EF h003EF h004EF h005EF h006EF h007EF h008EF h009EF h00AEF h00BEF h00CEF h00DEF h00EEF h00FEF h010EF h011EF h012EF h013EF
Rev.1.21 April 9, 2007, page 41 of 205
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R61505U Table 16 GRAM address and display position on the panel (SS = 1, BGR = 1)
S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 : h130EF h131EF h132EF h133EF h134EF h135EF h136EF h137EF h138EF h139EF h13AEF h13BEF h13CEF h13DEF h13EEF h13FEF S1 S/G pin GS=0 GS=1 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 : G305 G306 G307 G308 G309 G310 G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 G310 G309 G308 G307 G306 G305 G304 G303 G302 G301 : G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 S709 ...... ..... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... : ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ......
WD[17:0] h00000 h00100 h00200 h00300 h00400 h00500 h00600 h00700 h00800 h00900 h00A00 h00B00 h00C00 h00D00 h00E00 h00F00 h01000 h01100 h01200 h01300 : h13000 h13100 h13200 h13300 h13400 h13500 h13600 h13700 h13800 h13900 h13A00 h13B00 h13C00 h13D00 h13E00 h13F00
WD[17:0] h00001 h00101 h00201 h00301 h00401 h00501 h00601 h00701 h00801 h00901 h00A01 h00B01 h00C01 h00D01 h00E01 h00F01 h01001 h01101 h01201 h01301 : h13001 h13101 h13201 h13301 h13401 h13501 h13601 h13701 h13801 h13901 h13A01 h13B01 h13C01 h13D01 h13E01 h13F01
WD[17:0] h00002 h00102 h00202 h00302 h00402 h00502 h00602 h00702 h00802 h00902 h00A02 h00B02 h00C02 h00D02 h00E02 h00F02 h01002 h01102 h01202 h01302 : h13002 h13102 h13202 h13302 h13402 h13502 h13602 h13702 h13802 h13902 h13A02 h13B02 h13C02 h13D02 h13E02 h13F02
WD[17:0] h00003 h00103 h00203 h00303 h00403 h00503 h00603 h00703 h00803 h00903 h00A03 h00B03 h00C03 h00D03 h00E03 h00F03 h01003 h01103 h01203 h01303 : h13003 h13103 h13203 h13303 h13403 h13503 h13603 h13703 h13803 h13903 h13A03 h13B03 h13C03 h13D03 h13E03 h13F03
WD[17:0] h000EC h001EC h002EC h003EC h004EC h005EC h006EC h007EC h008EC h009EC h00AEC h00BEC h00CEC h00DEC h00EEC h00FEC h010EC h011EC h012EC h013EC : h130EC h131EC h132EC h133EC h134EC h135EC h136EC h137EC h138EC h139EC h13AEC h13BEC h13CEC h13DEC h13EEC h13FEC
WD[17:0] h000ED h001ED h002ED h003ED h004ED h005ED h006ED h007ED h008ED h009ED h00AED h00BED h00CED h00DED h00EED h00FED h010ED h011ED h012ED h013ED : h130ED h131ED h132ED h133ED h134ED h135ED h136ED h137ED h138ED h139ED h13AED h13BED h13CED h13DED h13EED h13FED
WD[17:0] h000EE h001EE h002EE h003EE h004EE h005EE h006EE h007EE h008EE h009EE h00AEE h00BEE h00CEE h00DEE h00EEE h00FEE h010EE h011EE h012EE h013EE : h130EE h131EE h132EE h133EE h134EE h135EE h136EE h137EE h138EE h139EE h13AEE h13BEE h13CEE h13DEE h13EEE h13FEE
WD[17:0] h000EF h001EF h002EF h003EF h004EF h005EF h006EF h007EF h008EF h009EF h00AEF h00BEF h00CEF h00DEF h00EEF h00FEF h010EF h011EF h012EF h013EF
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R61505U
Instruction
Outline The R61505U adopts 18-bit bus architecture in order to interface to high-performance microcomputer in high speed. The R61505U starts internal processing after storing control information (16, 8, 1 bit(s)), sent from the microcomputer, in the instruction register (IR) and the data register (DR). Since the internal operation of the R61505U is controlled by the signals sent from the microcomputer, the register selection signal (RS), the read/write signal (R/W), and the internal 16-bit data bus signals (IB15 ~ IB0) are called instruction. The following are the kinds of instruction of the R61505U. 1. 2. 3. 4. 5. 6. 7. 8. Specify index Display control Power management control Set internal GRAM address Transfer data to and from the internal GRAM -correction Window address control Panel Display Control
Normally, the instruction to write data is used the most often. The internal GRAM address is updated automatically as data is written to the internal GRAM, which, in combination with the window address function, contributes to minimizing data transfer and thereby lessens the load on the microcomputer. The R61505U writes instructions consecutively by executing the instruction within the cycle when it is written (instruction execution time: 0 cycle). Instruction Data Format As the following figure shows, the data bus used to transfer 16 instruction bits (IB[15:0]) is different according to the interface format. Make sure to transfer the instruction bits according to the format of the selected interface.
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R61505U The following are detail descriptions of instruction bits (IB15-0). Note that the instruction bits IB[15:0] in the following figures are transferred according to the format of the selected interface. Index (IR)
R/W W RS 0 IB15 * IB14 * IB13 * IB12 * IB11 * IB10 * IB9 * IB8 * IB7 ID [7] IB6 ID [6] IB5 ID [5] IB4 ID [4] IB3 ID [3] IB2 ID [2] IB1 ID [1] IB0 ID [0]
The index register specifies the index R00h to RFFh of the control register or RAM control to be accessed using a binary number from "0000_0000" to "1111_1111". The access to the register and instruction bits in it is prohibited unless the index is specified in the index register. Display control Device code read (R00h)
R/W R RS 1 IB15 0 IB14 0 IB13 0 IB12 1 IB11 0 IB10 1 IB9 0 IB8 1 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 1 IB1 0 IB0 1
The device code "1505"H is read out when reading out this register forcibly.
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R61505U Driver Output Control (R01h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 SM 0 IB9 0 0 IB8 SS 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 0 0 IB2 0 0 IB1 0 0 IB0 0 0
Default value
SS: Sets the shift direction of output from the source driver. When SS = "0", the source driver output shift from S1 to S720. When SS = "1", the source driver output shift from S720 to S1. The combination of SS and BGR settings determines the RGB assignment to the source driver pins S1 ~ S720. When SS = "0" and BGR = "0", RGB dots are assigned one to one from S1 to S720. When SS = "1" and BGR = "1", RGB dots are assigned one to one from S720 to S1. When changing the SS and BGR bits, RAM data must be rewritten. SM: Controls the scan mode in combination with GS setting. See " Scan mode setting". LCD Driving Wave Control (R02h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 1 1 IB9 BC0 0 IB8 EOR 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 0 0 IB2 0 0 IB1 0 0 IB0 NW0 0
Default value
NW0: When line inversion waveform is selected (BC0=1), NW0 bit sets number of line, N, as alternating cycle of line inversion. Line inversion is operated every N+1 line cycle. NW0 bit can be set to 1 or 2. BC0: Selects the liquid crystal drive waveform VCOM. See "Line Inversion AC Drive" for details. BC0 = 0: frame inversion waveform is selected. BC0 = 1: line inversion waveform is selected when EOR = 1. In either liquid crystal drive method; the polarity inversion is halted in blank period (back and front porch periods). EOR: Enables liquid-crystal line-inversion drive when EOR = 1 and BC0 = 1
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R61505U Entry Mode (R03h)
R/W W RS 1 IB15 IB14 IB13 TRIR DFM 0 EG 0 0 0 IB12 BGR 0 IB11 0 0 IB10 0 0 IB9 HWM 0 IB8 0 0 IB7 ORG 0 IB6 0 0 IB5 I/D [1] 1 IB4 I/D [0] 1 IB3 AM 0 IB2 0 0 IB1 0 0 IB0 0 0
Default value
The entry mode register includes instruction bits for setting how to write data from the microcomputer to the internal GRAM of the R61505U. AM: Sets either horizontal or vertical direction in updating the address counter automatically as the R61505U writes data to the internal GRAM. AM = "0", sets the horizontal direction. AM = "1", sets the vertical direction. When making a window address area, the data is written only within the area in the direction determined by I/D1-0, AM bits. I/D[1:0]: Either increments (+1) or decrements (-1) the address counter (AC) automatically as the data is written to the GRAM. The I/D[0] bit sets either increment or decrement in horizontal direction (updates the address AD[7:0]). The I/D[1] bit sets either increment or decrement in vertical direction (updates the address AD[8:16]). The AM bit sets either horizontal or vertical direction in updating RAM address counter automatically when writing data to the internal RAM. ORG: Moves the origin address according to the ID setting when a window address area is made. This function is enabled when writing data within the window address area using high-speed RAM write function. Also see Figure 3 and Figure 4. ORG = 0: The origin address is not moved. In this case, specify the address to start write operation according to the GRAM address map within the window address area. ORG = 1: The origin address "h00000" is moved according to the I/D[1:0] setting. Notes: 1. When ORG = 1, only the origin address "h00000" can be set in the RAM address set registers (R20h, R21h). 2. In RAM read operation, make sure to set ORG = 0. HWM: The R61505U writes data in high speed with low power consumption by setting HWM = 1. The data to be written within the window address area is buffered in order to write the data in units of horizontal lines. This can minimize the number of RAM access and the power consumption required in data write operation. When HWM = 1, make sure to set AM = 0 (horizontal direction) and write the data in each horizontal line of the window address area at a time. If the data is not enough to rewrite the horizontal line of the window address area, the GRAM data in that line is not overwritten. Notes: 1. The R61505U requires no dummy write operation in high-speed write operation. 2. When terminating RAM data write operation in the middle of the line and executing another instruction, the data in the buffer is cleared.
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R61505U 3. When switching from high-speed RAM write operation to index write operation, wait at least 2 normal-write cycle periods (2 tcycw periods). BGR: Reverses the order from RGB to BGR in writing 18-bit pixel data in the GRAM. BGR = 0: BGR = 1: BGR = 0
D17 R5 D16 R4 D15 R3 D14 R2 D13 R1 D12 R0 D11 G5 D10 G4 D9 G3 D8 G2 D7 G1 D6 G0 D5 B5 D4 B4 D3 B3 D2 B2 D1 B1 D0 B0
Write data in the order of RGB to the GRAM. Reverse the order from RGB to BGR in writing data to the GRAM.
BGR = 1
D17 B5 D16 B4 D15 B3 D14 B2 D13 B1 D12 B0 D11 G5 D10 G4 D9 G3 D8 G2 D7 G1 D6 G0 D5 R5 D4 R4 D3 R3 D2 R2 D1 R1 D0 R0
DFM: In combination with the TRIREG setting, sets the format to develop 16-/8-bit data to 18-bit data when using either 16-bit or 8-bit bus interface. Make sure to set DFM = 0 when not transferring data via 16-bit or 8-bit interface. TRIREG: Selects the format to transfer data bits via 16-bit or 8-bit interface. In 8-bit interface operation, TRIREG = 0: 16-bit RAM data is transferred in two transfers. TRIREG = 1: 18-bit RAM data is transferred in three transfers. In 16-bit bus interface operation, TRIREG = 0: 16-bit RAM data is transferred in one transfer. TRIREG = 1: 18-bit RAM data is transferred in two transfers. Make sure TRIREG = 0 when not transferring data via 16-bit or 8-bit interface. Also, set TRIREG = 0 during read operation.
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R61505U
ORG = 0
I/D1-0 = "00" Horizontal: Decrement Vertical: Decrement
17'h00000
I/D1-0 = "01" Horizontal: Increment Vertical: Decrement
17'h00000
I/D1-0 = "10" Horizontal: Decrement Vertical: Increment
17'h00000
I/D1-0 ="11" Horizontal: Increment Vertical: Increment
17'h00000
AM = "0" Horizontal
17'h13FEF 17'h00000 17'h00000
17'h13FEF 17'h00000
17'h13FEF 17'h00000
17'h13FEF
AM = "1" Vertical
17'h13FEF
17'h13FEF
17'h13FEF
17'h13FEF
Figure 3 Automatic address update (ORG = 0, AM, ID) Note: When writing data within the window address area with ORG = 0, any address within the window address area can be designated as the starting point of RAM write operation.
ORG = 1
I/D1-0 = "00" Horizontal: Decrement Vertical: Decrement
17'h00000
I/D1-0 = "01" Horizontal: Increment Vertical: Decrement
17'h00000
I/D1-0 = "10" Horizontal: Decrement Vertical: Increment
17'h00000
I/D1-0 = "11" Horizontal: Increment Vertical: Increment
17'h00000
S AM = "0" Horizontal S
17'h13FEF 17'h00000 17'h00000
S
S
17'h13FEF 17'h00000 17'h13FEF 17'h00000 17'h13FEF
S AM = "1" Vertical S
17'h13FEF
S
S
17'h13FEF 17'h13FEF 17'h13FEF
Figure 4 Automatic address update (ORG = 1, AM, ID) Notes: 1. When ORG = 1, make sure to set the address "h00000" in the RAM address set registers (R210h, R21h). Setting other addresses is inhibited. 2. When ORG = 1, the starting point of writing data within the window address area can be set at either corner of the window address area ("S" in circle in the above figure).
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R61505U Resizing Control (R04h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 IB8 RCV RCV [1] [0] 0 0 IB7 0 0 IB6 0 0 IB5 IB4 RCH RCH [1] [0] 0 0 IB3 0 0 IB2 0 0 IB1 RSZ [1] 0 IB0 RSZ [0] 0
Default value
RSZ[1:0]: Sets the resizing factor. When the RSZ bits are set for resizing, the R61505U writes the data according to the resizing factor so that the original image is displayed in horizontal and vertical dimensions contracted according to the factor . See "Resizing function". RCH[1:0]: Sets the number of pixels made as the remainder in horizontal direction when resizing a picture. By specifying the number of remainder pixels with RCH bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCH = 2'h0 when not using the resizing function (RSZ = 2'h0) or there are no remainder pixels. RCV[1:0]: Sets the number of pixels made as the remainder in vertical direction when resizing a picture. By specifying the number of remainder pixels with the RCV bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCV = 2'h0 when not using the resizing function (RSZ = 2'h0). Table 17 Resizing factor (RSR)
RSZ [1:0] 2'h0 2'h1 2'h2 2'h3 Resizing Scale No resizing (x1) x 1/2 Setting inhibited x 1/4
Table 18 Remainder Pixels in Horizontal Direction (RCH)
RCH [1:0] 2'h0 2'h1 2'h2 2'h3 Note: 1 pixel = 1RGB Number of remainder Pixels in Horizontal Direction 0 pixel 1 pixel 2 pixels 3 pixels
Table 19 Remainder Pixels in Vertical Direction (RCV)
RCV [1:0] 2'h0 2'h1 2'h2 2'h3 Note: 1 pixel = 1RGB Number of remainder Pixels in Vertical Direction 0 pixel 1 pixel 2 pixels 3 pixels
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R61505U Display Control 1 (R07h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 IB12 IB11 PTDE PTDE 0 [1] [0] 0 0 0 IB10 0 0 IB9 0 0 IB8 BASE E 0 IB7 0 0 IB6 VON 0 IB5 GON 0 IB4 DTE 0 IB3 COL 0 IB2 0 0 IB1 D [1] 0 IB0 D [0] 0
Default value
D[1:0]: A graphics display is turned on when writing D1 = "1", and is turned off when writing D1 = "0". When writing D1 = "0", the graphics display data is retained in the internal GRAM and the R61505U displays the data when writing D1 = "1". When D1 = "0", i.e. while no display is shown on the panel, all source outputs becomes the GND level to reduce charging/discharging current, which is generated within the LCD while driving liquid crystal with AC voltage. When the display is turned off by setting D1-0 = 2'b01, the R61505U continues internal display operation. When the display is turned off by setting D1-0 = 2'b00, the R61505U's internal display operation is halted completely. In combination with the GON setting, the D[1:0] setting controls display ON/OFF. For details, see "Instruction Setting". Table 20 Source output level and display operation
D[1:0] 2'h0 2'h1 2'h2 2'h3 BASEE * * * 0 1 Source Output (S1-720) GND GND Non-lit display Non-lit display Base-image display FMARK signal Halt Operation Operation Operation Operation Internal Operation Halt Operation Operation Operation Operation
Notes: 1: The data write operation from the microcomputer is not affected by the D[1:0] setting. 2: The PTS bits set the source output level for "Non-lit display". 3: The LCD drive level during non-lit display period is determined by NDL setting. COL: When COL = 1, 30 grayscale amplifiers other than V0 and V30 halt to display using less power. When setting 8-color display mode, follow the sequence of 8-color display mode setting. Table 21
COL 0 1 Operating amplifier 32 2 Display color 262,144 8
Note: When COL = 1, do not write the data corresponding to the grayscales, for which the operation of amplifier is halted.
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R61505U GON, DTE: The combination of GON and DTE settings set the output level form gate lines (G1 ~ G320). When GON = 0, the VCOM output level becomes the GND level. Table 22
APE 0 GON *
0 0 1 1
DTE *
0 1 0 1
G1~G320 VGL (= GND) VGH VGH VGL VGH/VGL
1
VON: Controls VCOMH, VCOML, VCOM amplitude signal output. Table 23
APE 0 AP[1:0] *
0 0 1~3 1~3
VON * 0 1 0 1
VCOM output GND GND
Setting disabled
1
GND
VCOMH/VCOML
BASEE: Base image display enable bit. BASEE = 0: No base image is displayed. The R61505U drives liquid crystal with non-lit display level or drives only partial image display areas. BASEE = 1: A base image is displayed on the screen. The D[1:0] setting has precedence over the BASEE setting. PTDE[1:0]: PTDE[0] is the display enable bit of partial image 1. PTDE[1] is the display enable bit of partial image 2. When PTDE1/0 = 0, the partial image is turned off and only base image is displayed on the screen. When PTDE1/0 = 1, the partial image is displayed on the screen. In this case, turn off the base image by setting BASEE = 0.
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R61505U Display Control 2 (R08h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 FP [3] 1 IB10 FP [2] 0 IB9 FP [1] 0 IB8 FP [0] 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 BP [3] 1 IB2 BP [2] 0 IB1 BP [1] 0 IB0 BP [0] 0
Default value
FP [3:0]: Sets the number of lines for a front porch period (a blank period following the end of display). BP [3:0]: Sets the number of lines for a back porch period (a blank period made before the beginning of display). In external display interface operation, a back porch (BP) period starts on the falling edge of the VSYNC signal and the display operation starts after the back porch period. A blank period will start after a front porch (FP) period and it will continue until next VSYNC input is detected.
Note to Setting BP and FP
Set the BP and FP bits as follows in respective operation modes. Table 24 BP and FP Settings
Internal clock operation mode RGB interface operation VSYNC interface operation BP 2 lines BP 2 lines BP 2 lines FP 2 lines FP 2 lines FP 2 lines FP + BP 16 lines FP + BP 16 lines FP + BP = 16 lines
Table 25 Front and Back Porch period (Line periods)
FP[3:0] BP[3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF Front and Back Porch period (Line periods) Setting inhibited Setting inhibited 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines Setting inhibited
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R61505U
VSYNC Back porch
Display area
Front porch
Note : The output timing to the LCD panel is delayed by two line periods from the synchronous signal (VSYNC) input timing.
Figure 5 Front and Back Porch periods
Display Control 3 (R09h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 PTS [2] 0 IB9 PTS [1] 0 IB8 PTS [0] 0 IB7 0 0 IB6 0 0 IB5 PTG [1] 0 IB4 PTG [0] 0 IB3 ISC [3] 0 IB2 ISC [2] 0 IB1 ISC [1] 0 IB0 ISC [0] 0
Default value
ISC [3:0]: Set the scan cycle when PTG[1:0] selects interval scan in non-display area drive period. The scan cycle is defined by n frame periods, where n is an odd number from 3 to 31. The polarity of liquid crystal drive voltage from the gate driver is inverted in the same timing as the interval scan cycle. Table 26
ISC[3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 Scan cycle Setting disabled 3 frames 5 frames 7 frames 9 frames 11 frames 13 frames 15 frames
Time for interval when (fFLM) = 60Hz
ISC[3:0] 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF
Scan cycle 17 frames 19 frames 21 frames 23 frames 25 frames 27 frames 29 frames 31 frames
Time for interval when (fFLM) = 60Hz
50ms 84ms 117ms 150ms 184ms 217ms 251ms
284ms 317ms 351ms 384ms 418ms 451ms 484ms 518ms
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R61505U PTG[1:0]: Sets the scan mode in non-display area. The scan mode selected by PTG[1:0] bits is applied in the non-display area when the base image is turned off and the non-display area other than the first and second partial display areas. Table 27
PTG[1] 0 0 1 1 PTG[0] 0 1 0 1 Scan mode in nondisplay area Normal scan Setting disabled Interval scan Setting disabled Source output level in non-display area PTS[2:0] setting PTS[2:0] setting VCOM output VCOMH/VCOML amplitude VCOMH/VCOML amplitude -
Note: Select frame-inversion AC drive when interval scan is selected.
PTS[2:0]: Sets the source output level in non-display area drive period. When PTS[2] = 1, the operation of amplifiers which generates the grayscales other than V0 and V31 are halted and the step-up clock frequency becomes half the normal frequency in non-display drive period in order to reduce power consumption. Table 28 Source output level and voltage generating operation in non-display drive period
PTS[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 Source output level Positive polarity Negative polarity V31 Setting inhibited GND Hi-Z V31 Setting inhibited GND Hi-Z V0 Setting inhibited GND Hi-Z V0 Setting inhibited GND Hi-Z Grayscale amplifier in operation V0 to V31 V0 to V31 V0 to V31 V0 and V31 V0 and V31 V0 and V31 Step-up clock frequency
Register setting (DC0, DC1) Register setting (DC0, DC1) Register setting (DC0, DC1) 1/2 the frequency set by DC0, DC1
1/2 the frequency set by DC0, DC1 1/2 the frequency set by DC0, DC1
Notes: 1. The power efficiency improved by halting grayscale amplifiers and slowing down the step-up clock frequency can be obtained in non-display drive period. 2. The gate output level in non-display drive period is controlled by the PTG setting (off-scan mode).
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R61505U Display Control 4 (R0Ah)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 0 0 IB8 0 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 IB2 FMAR FMI KOE [2] 0 0 IB1 FMI [1] 0 IB0 FMI [0] 0
Default value
FMI[2:0]: Sets the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate. FMARKOE: When FMARKOE = 1, the R61505U starts outputting FMARK signal from the FMARK pin in the output interval set by FMI[2:0] bits. See FMARK Interface" for details. Table 29
FMI[2] 0 0 0 1 FMI[1] 0 0 1 0 FMI[0] 0 1 1 1 Output interval 1 frame 2 frames 4 frames 6 frames Setting disabled
Other settings
External Display Interface Control 1 (R0Ch)
R/W W RS 1 IB15 0 0 IB14 ENC [2] 0 IB13 ENC [1] 0 IB12 ENC [0] 0 IB11 0 0 IB10 0 0 IB9 0 0 IB8 RM 0 IB7 0 0 IB6 0 0 IB5 DM [1] 0 IB4 DM [0] 0 IB3 0 0 IB2 0 0 IB1 RIM [1] 0 IB0 RIM [0] 0
Default value
RIM[1:0]: Sets the interface format when RGB interface is selected by RM and DM bits. Set RIM[1:0] bits before starting display operation via RGB interface. Do not change the setting while the R61505U performs display operation. Table 30 RGB interface operation
RIM[1:0] 2'h0 2'h1 2'h2 2'h3 RGB Interface operation 18-bit RGB interface (1 transfer/pixel) via DB17-0 16-bit RGB interface (1 transfer/pixel) via DB17-13 and DB11-1 6-bit RGB interface (3 transfers/pixel) via DB17-12 Setting inhibited Colors 262,144 65,536 262,144 -
Notes: 1: Instruction bits are set via system interface. 2: Transfer the RGB dot data one by one in synchronization with DOTCLK in 6-bit RGB interface operation.
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R61505U DM[1:0]: Selects the interface for the display operation. The DM[1:0] setting allows switching between internal clock operation mode and external display interface operation mode. However, switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited. Table 31 Display Interface
DM[1:0] 2'h0 2'h1 2'h2 2'h3 Display Interface Internal clock operations RGB interface VSYNC interface Setting inhibited
RM: Selects the interface for RAM access operation. RAM access is possible only via the interface selected by the RM bit. Set RM = 1 when writing display data via RGB interface. When RM = 0, it is possible to write data via system interface while performing display operation via RGB interface. Table 32 RAM Access Interface
RM 0 1 RAM Access Interface System interface/VSYNC interface RGB interface
ENC[2:0]: Sets the RAM write cycle via RGB interface. Table 25 RAM Write Cycle
ENC[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 RAM Write Cycle (frame periods) 1 frame 2 frames 3 frames 4 frames 5 frames 6 frames 7 frames 8 frames
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R61505U Frame Marker Position (R0Dh)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 0 0 IB8 FMP [8] 0 IB7 FMP [7] 0 IB6 FMP [6] 0 IB5 FMP [5] 0 IB4 FMP [4] 0 IB3 FMP [3] 0 IB2 FMP [2] 0 IB1 FMP [1] 0 IB0 FMP [0] 0
Default value
FMP[8:0]: Sets the output position of frame cycle signal (frame marker). When FMP[8:0] = 9'h000, a high-active pulse FMARK is outputted at the start of back porch period for 1H period (IOVCC-IOGND amplitude signal). FMARK can be used as the trigger signal for frame synchronous write operation. See FMARK Interface for details. Make sure the setting restriction 9'h000 FMP BP+NL+FP. Table 33
FMP[8:0] 9''h000 9'h001 9''h002 : 9''h14E 9'h14F 9''h150~1FF FMARK output position 0 line 1 line 2nd line : 334th line 335th line Setting disabled
st th
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R61505U VCOM Low Power Control (R0Eh)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 0 0 0 0 0 0 IB9 0 0 IB8 0 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 IB3 VEM 0 [0] 0 0 IB2 0 0 IB1 0 0 IB0 0 0
Default value
VEM [0]: VCOM equalize function control bit. When VEM [0]="1", VCOM connect to GND when switching to VCOMH to VCOML (VCOMH GND VCOML). Adjust VCOM equalize period by setting VEQWI[2:0] (R93h) after setting VEM[0]1. Less power is consumed when VCOM equalize function is used compared with normal VCOM drive. Check image quality and effectiveness of the function. Make sure that VCIVCOML. Table 34
VEM[0] 1'h0 1'h1 Operation Normal VCOM drive Equalize VCOML (VCOMHVCOML)
Note: This function is disabled when RGB interface is selected.
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R61505U External Display Interface Control 2 (R0Fh)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 0 0 IB8 0 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 IB3 IB2 0 0 IB1 EPL 0 IB0 DPL 0 VSPL HSPL 0 0
Default value
DPL: Sets the signal polarity of DOTCLK pin. DPL = 0: input data on the rising edge of DOTCLK DPL = 1: input data on the falling edge of DOTCLK EPL: Sets the signal polarity of ENABLE pin. EPL = 0: writes data DB17-0 when ENABLE = "0" and disables data write operation when ENABLE = "1". EPL = 1: writes data DB17-0 when ENABLE = "1" and disables data write operation when ENABLE = "0". HSPL: Sets the signal polarity of HSYNC pin. HSPL = 0: low active HSPL = 1: high active VSPL: Sets the signal polarity of VSYNC pin. VSPL = 0: low active VSPL = 1: high active
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R61505U Power control Power Control 1 (R10h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 SAP SAP SAP [1] [0] 0 0 0 0 0 BT [2] 0 IB9 BT [1] 0 IB8 BT [0] 0 IB7 APE 0 IB6 AP [2] 0 IB5 AP [1] 0 IB4 AP [0] 0 IB3 0 0 IB2
DSTB
IB1 SLP 0
IB0 0 0
Default value
0
SLP: When SLP = 1, the R61505U enters the sleep mode. In sleep mode, the internal display operation except RC oscillation is halted to reduce power consumption. No change to the GRAM data and instruction setting is accepted and he GRAM data and the instruction setting are maintained in sleep mode. DSTB: When DSTB = 1, the R61505U enters the deep standby mode. In deep standby mode, the internal logic power supply is turned off to reduce power consumption. The GRAM data and instruction setting are not maintained when the R61505U enters the deep standby mode, and they must be reset after exiting deep standby mode. AP[2:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit. The larger constant current enhances the drivability of the LCD, but it also increases the current consumption. Adjust the constant current taking the trade-off into account between the display quality and the current consumption. In no-display period, set AP[2-0] = 3'h0 to halt the operational amplifier circuits and the step-up circuits to reduce current consumption. Table 35 Constant current in amplifier in LCD power supply
AP[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 LCD power supply circuits Halt operation Setting disabled Setting disabled 1 Setting disabled Setting disabled Setting disabled 1.60
Note: In this table, the constant current in operational amplifiers is the ratio to the constant current when AP[2:0] is set to 3'h3.
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R61505U APE: Liquid crystal power supply enable bit. Set APE = 1 and follow the sequence when starting up the liquid crystal power supply. Table 36
APE 0 1 Liquid crystal power supply circuit Halt Operate Grayscale voltage generating circuit Halt Operate
BT[2:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor. Table 37 Step up factor and output voltage level
BT[2:0]
3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 DDVDH x 3 [x 6] VCI1 x 2 [x 2] -VCI1 [x -1] VCI1+DDVDH x 3 [x 7]
DDVDH
VCL
VGH
DDVDH x 3 [x 6] DDVDH x 4 [x 8]
VGL
-(VCI1+DDVDH x 2) [x -5] -(DDVDHx2) [x -4] -(VCI1+DDVDH) [x -3]
Capacitor connection pin (see note 4)
C23 may be omitted.
-(VCI1+DDVDH x 2) [x -5] -(DDVDHx2) [x -4] [x -3] C23 may be omitted. C23 may be omitted.
-(VCI1+DDVDH) -(DDVDHx2)
[x -4] [x -3]
-(VCI1+DDVDH)
Notes: 1. The step-up factor from VCI1 is shown in the brackets [ ]. 2. Connect capacitors where required when using DDVDH, VGH, VGL and VCL voltages. 3. Set the following voltages within the respective ranges: DDVDH = 6.0V (max.) VGH = 20.0V (max.) VGL = -13.5V (max.) VCL=-3.0V(max.) 4. Connect capacitors according to "Specifications of Power-supply Circuit External Elements". In this case, comments should be preceded.
SAP: The grayscale voltage generating circuit is halted by setting SAP = 0. Grayscale voltages are generated when SAP = 1. When starting the operation of LCD power supply circuit in Power ON operation and so on, make sure SAP = 0. Set SAP = 1, after starting up the LCD power supply circuit. SAP[1:0]: Adjusts constant current in the grayscale voltage generating circuit . Note that VC and AP bits must be taken into consideration when setting SAP[1:0] bit: When VC=3'h7, set AP[2:0]=3'h3 and SAP[1:0]=2'h0 When VC 3'h7, set AP[2:0]=3'h7,SAP[1:0]=2'h3
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R61505U Power Control 2 (R11h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 DC1 [2] 1 IB9 DC1 [1] 1 IB8 DC1 [0] 0 IB7 0 0 IB6 DC0 [2] 1 IB5 DC0 [1] 1 IB4 DC0 [0] 0 IB3 0 0 IB2 VC [2] 0 IB1 VC [1] 0 IB0 VC [0] 0
Default value
Table 38 step-up frequency (Step-up Circuit 1)
DC0[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 Step-up circuit 1: step-up frequency (fDCDC1) fosc fosc / 2 fosc / 4 fosc / 8 fosc / 16 Setting inhibited Halt Step-up circuit 1 Setting inhibited
Note 1: Make sure the DC0, DC1 setting restriction: fDCDC1 fDCDC2. Note 2: fosc: RC oscillation frequency.
Table 39 step-up frequency (Step-up Circuit 2)
DC1[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 Step-up circuit 2: step-up frequency (fDCDC2) fosc / 16 fosc / 32 fosc / 64 fosc / 128 fosc / 256 Setting inhibited Halt Step-up circuit 2 Setting inhibited
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R61505U Table 40 VCIOUT output level
VC[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7
VCIOUT (Reference Voltage) (VCI1 Voltage) 0.94 x VCILVL 0.89 x VCILVL 0.84 x VCILVL Setting inhibited Setting inhibited Setting inhibited 0.7 x VCILVL 1.00 x VCILVL Note 3 Note 4
Note 3: This setting is allowed only during the power ON sequence. However, when the electrical potential VCI is directly applied to VCI1 pin (connected on the substrate), setting VC=3'h6 is inhibited. See Power supply Instruction Setting for detail. Note 4: When VC=3'h7, set AP[2:0]=3'h3 and SAP[1:0]=2'h0. When VC3'h7, AP[2:0]=3'h7 and SAP[1:0]=2'h3.
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R61505U Power Control 3 (R12h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 0 0 IB8 VCM R[0] 0 IB7 VRE G1R 0 IB6 0 0 IB5 IB4 PSON PON 0 0 IB3 VRH [3] 0 IB2 VRH [2] 0 IB1 VRH [1] 0 IB0 VRH [0] 0
Default value
VRH[3:0]: Sets the factor to generate VREG1OUT from VCILVL. Table 41 VREG1OUT
VRH 4'h0 ~ 4'h3 4'h4 ~ 4'h7 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF VREG1OUT Voltage
(External Reference Electric potential; VCILVL)
VREG1OUT Voltage
Internal Reference Electric Potential; VCIR
Halt (Hiz) Setting inhibited VCILVLx1.60 VCILVLx1.65 VCILVLx1.70 VCILVLx1.75 VCILVLx1.80 VCILVLx1.85 VCILVLx1.90 Setting inhibited
HaltHiz Setting inhibited 2.5Vx1.60 = 4.00V 2.5Vx1.65 = 4.13V 2.5Vx1.70 = 4.25V 2.5Vx1.75 = 4.38V 2.5Vx1.80 = 4.50V 2.5Vx1.85 = 4.63V 2.5Vx1.90 = 4.75V Setting inhibited
Note:
Make sure the VC and VRH setting restrictions: VREG1OUT (DDVDH-0.5)V.
PON: Controls the operation to generate VLOUT3. In setting the PON bit, follows the power-supply startup sequence. PON = 0: Halts the step-up operation to generate VLOUT3. PON = 1: Starts the step-up operation to generate VLOUT3. PSON: Power supply ON bit. When turning on the power supply, set PSE = 1 first and then set PSON = 1 to start internal power supply operation. VREG1R: Set reference voltage to generate VREG1OUT. Table 42
VREG1R 0 (Default Value) 1 reference voltage for VREG1OUT VCILVL (External) VCIR (Internal Reference Voltage)
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R61505U VCMR[0]: Selects either external resistance (VCOMR pin) or internal electronic volume (VCM[4:0]) to set the electrical potential of VCOMH. The internal electronic volume can be set by VCM1 and VCM2 bits Table 43
VCMR[0] 0 1 VCOMH Electrical Potential setting VCOMR Internal electronic volume
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R61505U Power Control 4 (R13h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 VDV [4] 0 IB11 VDV [3] 0 IB10 VDV [2] 0 IB9 VDV [1] 0 IB8 VDV [0] 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 0 0 IB2 0 0 IB1 0 0 IB0 0 0
Default value
VDV[4:0]: Set VCOM alternating amplitude in the range of VREG1OUTx0.70 to VREG1OUTx1.24. Table 44 VDV Setting
VDV[4:0] 5'h0 5'h1 5'h2 5'h3 5'h4 5'h5 5'h6 5'h7 5'h8 5'h9 5'hA 5'hB 5'hC 5'hD 5'hE 5'hF VCOM Amplitude VREG1OUTx0.70 VREG1OUTx0.72 VREG1OUTx0.74 VREG1OUTx0.76 VREG1OUTx0.78 VREG1OUTx0.80 VREG1OUTx0.82 VREG1OUTx0.84 VREG1OUTx0.86 VREG1OUTx0.88 VREG1OUTx0.90 VREG1OUTx0.92 VREG1OUTx0.94 VREG1OUTx0.96 VREG1OUTx0.98 VREG1OUTx1.00 VDV[4:0] 5'h10 5'h11 5'h12 5'h13 5'h14 5'h15 5'h16 5'h17 5'h18 5'h19 5'h1A 5'h1B 5'h1C 5'h1D 5'h1E 5'h1F VCOM Amplitude VREG1OUTx0.94 VREG1OUTx0.96 VREG1OUTx0.98 VREG1OUTx1.00 VREG1OUTx1.02 VREG1OUTx1.04 VREG1OUTx1.06 VREG1OUTx1.08 VREG1OUTx1.10 VREG1OUTx1.12 VREG1OUTx1.14 VREG1OUTx1.16 VREG1OUTx1.18 VREG1OUTx1.20 VREG1OUTx1.22 VREG1OUTx1.24
Note:
Set VDV[4:0] so that VCOM amplitude becomes 6.0V or less.
Power Control 5 (R17h)
R/W W RS 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 0 0 IB8 0 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 0 0 IB2 0 0 IB1 0 0 IB0 PSE 0
Default value
PSE: Power supply startup enable bit. PSE = 1: The R61505U's power supply is started by setting PSON when PSE =1. When completing the power supply generating operation, PSE is set to 0.
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R61505U Power Control 6 (R19h)
IB 15 0 0 IB 14 0 0
R/W W
RS 1
IB13 IB12 IB11 IB10 0 0 0 0 0 0 0 0
IB9
IB8
IB7 0 0
IB6 0 0
IB5 0 0
IB4 0 0
IB3 0 0
IB2 0 0
IB1 0 0
IB0 0 0
TBT TBT [1] [0] 1 1
Default
TBT[1:0]: Sets position from where BT bit (R10h) is enabled by number of frame(s). Set TBT=2'h0 in Power Supply Instruction Setting, Deep Standby Exit Sequence and Sleep Mode Exit Sequence. See Power supply Instruction Setting.
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R61505U RAM access instruction RAM Address Set (Horizontal Address) (R20h) RAM Address Set (Vertical Address) (R21h)
R/W R 20 R 21 W RS 1 IB15 0 0 0 0 IB14 0 0 0 0 IB13 0 0 0 0 IB12 0 0 0 0 IB11 0 0 0 0 IB10 0 0 0 0 IB9 0 0 0 0 IB8 0 0 AD [16] 0 IB7 AD [7] 0 AD [15] 0 IB6 AD [6] 0 AD [14] 0 IB5 AD [5] 0 AD [13] 0 IB4 AD [4] 0 AD [12] 0 IB3 AD [3] 0 AD [11] 0 IB2 AD [2] 0 AD [10] 0 IB1 AD [1] 0 AD [9] 0 IB0 AD [0] 0 AD [8] 0
Default value
W
1
Default value
AD[16:0]: A GRAM address set initially in the AC (Address Counter). The address in the AC is automatically updated according to the combination of AM, I/D[1:0] settings as the R61505U writes data to the internal GRAM so that data can be written consecutively without resetting the address in the AC. The address is not automatically updated when reading data from the internal GRAM. Note 1: In RGB interface operation (RM = "1"), the address AD16-0 is set in the address counter every frame on the falling edge of VSYNC. Note 2: In internal clock operation and VSYNC interface operation (RM = "0"), the address AD16-0 is set when executing the instruction.
Table 45 GRAM Address setting range
AD[16:0] 17'h00000 - 17'h000EF 17'h00100 - 17'h001EF 17'h00200 - 17'h002EF 17'h00300 - 17'h003EF 17'h00400 - 17'h004EF : 17'h13600 - 17'h13CEF 17'h13700 - 17'h13DEF 17'h13800 - 17'h13EEF 17'h13900 - 17'h13FEF GRAM Data Setting Bitmap data on the first line Bitmap data on the second line Bitmap data on the third line Bitmap data on the fourth line Bitmap data on the fifth line : Bitmap data on the 317th line Bitmap data on the 318th line Bitmap data on the 319th line Bitmap data on the 320th line
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R61505U Write Data to GRAM (R22h)
R/W W RS 1 RAM write data WD[17:0] is transferred via different data bus in different interface operation. RAM write data WD[17:0] is transferred via different data bus in different interface operation.
RGB interface
WD[17:0]: The R61505U develops data into 18 bits internally in write operation. The format to develop data into 18 bits is different in different interface operation. The GRAM data represents the grayscale level. The R61505U automatically updates the address according to AM and I/D[1:0] settings as it writes data in the GRAM. The DFM bit sets the format to develop 16-bit data into the 18-bit data in 16-bit or 8-bit interface operation. Note: When writing data in the GRAM via system interface while using the RGB interface, make sure that write operations via two interfaces do not conflict one another.
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R61505U Table 46 GRAM data and corresponding LCD grayscale level (REV =1)
GRAM data RGB 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F Grayscale level Negative V31 (V30+V31)/2 V30 (V29+V30)/2 V29 (V28+V29)/2 V28 (V27+V28)/2 V27 (V26+V27)/2 V26 (V25+V26)/2 V25 (V24+V25)/2 V24 (V23+V24)/2 V23 (V22+V23)/2 V22 (V21+V22)/2 V21 (V20+V21)/2 V20 (V19+V20)/2 V19 (V18+V19)/2 V18 (V17+V18)/2 V17 (V16+V17)/2 V16 (V15+V16)/2 Positive V0 (V0+V1)/2 V1 (V1+V2)/2 V2 (V2+V3)/2 V3 (V3+V4)/2 V4 (V4+V5)/2 V5 (V5+V6)/2 V6 (V6+V7)/2 V7 (V7+V8)/2 V8 (V8+V9)/2 V9 (V9+V10)/2 V10 (V10+V11)/2 V11 (V11+V12)/2 V12 (V12+V13)/2 V13 (V13+V14)/2 V14 (V14+V15)/2 V15 (V15+V16)/2 GRAM data RGB 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 6'h29 6'h2A 6'h2B 6'h2C 6'h2D 6'h2E 6'h2F 6'h30 6'h31 6'h32 6'h33 6'h34 6'h35 6'h36 6'h37 6'h38 6'h39 6'h3A 6'h3B 6'h3C 6'h3D 6'h3E 6'h3F Grayscale level Negative V15 (V14+V15)/2 V14 (V13+V14)/2 V13 (V12+V13)/2 V12 (V11+V12)/2 V11 (V10+V11)/2 V10 (V9+V10)/2 V9 (V8+V9)/2 V8 (V7+V8)/2 V7 (V6+V7)/2 V6 (V5+V6)/2 V5 (V4+V5)/2 V4 (V3+V4)/2 V3 (V2+V3)/2 V2 (V1+V2)/2 V1 (V0+V1)/2 (V1+2V0)/3 V0 Positive V16 (V16+V17)/2 V17 (V17+V18)/2 V18 (V18+V19)/2 V19 (V19+V20)/2 V20 (V20+V21)/2 V21 (V21+V22)/2 V22 (V22+V23)/2 V23 (V23+V24)/2 V24 (V24+V25)/2 V25 (V25+V26)/2 V26 (V26+V27)/2 V27 (V27+V28)/2 V28 (V28+V29)/2 V29 (V29+V30)/2 V30 (V30+V31)/2 (V30+2V31)/3 V31
Note: (Vn+Vn+1)/2, (V1+2V0)/3 and (V30+2V31)/3 are the effective grayscale levels by FRC (frame rate control).
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R61505U Table 47 GRAM data and corresponding LCD grayscale level (REV =0)
GRAM data RGB 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F Grayscale level Negative V0 (V0+V1)/2 V1 (V1+V2)/2 V2 (V2+V3)/2 V3 (V3+V4)/2 V4 (V4+V5)/2 V5 (V5+V6)/2 V6 (V6+V7)/2 V7 (V7+V8)/2 V8 (V8+V9)/2 V9 (V9+V10)/2 V10 (V10+V11)/2 V11 (V11+V12)/2 V12 (V12+V13)/2 V13 (V13+V14)/2 V14 (V14+V15)/2 V15 (V15+V16)/2 Positive V31 (V30+V31)/2 V30 (V29+V30)/2 V29 (V28+V29)/2 V28 (V27+V28)/2 V27 (V26+V27)/2 V26 (V25+V26)/2 V25 (V24+V25)/2 V24 (V23+V24)/2 V23 (V22+V23)/2 V22 (V21+V22)/2 V21 (V20+V21)/2 V20 (V19+V20)/2 V19 (V18+V19)/2 V18 (V17+V18)/2 V17 (V16+V17)/2 V16 (V15+V16)/2 GRAM data RGB 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 6'h29 6'h2A 6'h2B 6'h2C 6'h2D 6'h2E 6'h2F 6'h30 6'h31 6'h32 6'h33 6'h34 6'h35 6'h36 6'h37 6'h38 6'h39 6'h3A 6'h3B 6'h3C 6'h3D 6'h3E 6'h3F Grayscale level Negative V16 (V16+V17)/2 V17 (V17+V18)/2 V18 (V18+V19)/2 V19 (V19+V20)/2 V20 (V20+V21)/2 V21 (V21+V22)/2 V22 (V22+V23)/2 V23 (V23+V24)/2 V24 (V24+V25)/2 V25 (V25+V26)/2 V26 (V26+V27)/2 V27 (V27+V28)/2 V28 (V28+V29)/2 V29 (V29+V30)/2 V30 (V30+V31)/2 (V30+2V31)/3 V31 Positive V15 (V14+V15)/2 V14 (V13+V14)/2 V13 (V12+V13)/2 V12 (V11+V12)/2 V11 (V10+V11)/2 V10 (V9+V10)/2 V9 (V8+V9)/2 V8 (V7+V8)/2 V7 (V6+V7)/2 V6 (V5+V6)/2 V5 (V4+V5)/2 V4 (V3+V4)/2 V3 (V2+V3)/2 V2 (V1+V2)/2 V1 (V0+V1)/2 (V1+2V0)/3 V0
Note: (Vn+Vn+1)/2, (V1+2V0)/3, (V30+2V31)/3 are the effective grayscale levels by FRC (frame rate control).
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R61505U Read Data from GRAM (R22h)
R/W R RS 1 RAM read data RD[17:0] is transferred via different data bus in different interface operation.
RD[17:0]: 18-bit data read from the GRAM. RAM read data RD[17:0] is transferred via different data bus in different interface operation. When the R61505U reads data from the GRAM to the microcomputer, the first word read immediately after RAM address set is not outputted, so that it is invalid. Valid data is sent to the data bus when the R61505U reads out the second and subsequent words. When either 8-bit or 16-bit interface is selected, the LSBs of R and B dot data are not read out. Note: This register is not available in RGB interface operation.
Set I/D, AM, HSA, HEA, VSA, and VEA bits
Set address N
First word
Dummy read (invalid data) GRAM data read data latch Read (data of address N) Read data latch DB17-0
Second word
Set address M
First word
Dummy read (invalid data) GRAM data read data latch Read (data of address M) Read data latch DB17-0
Second word
Read out data to microcomputer
Figure 6 GRAM Read Sequence
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R61505U NVM(NON-VOLATILE MEMORY) write control instruction NVM read data (R28h), VCOM High Voltage (R29h, R2Ah)
R/W R28 W RS 1 IB15 0 0 0 0 0 0 IB14 0 0 0 0 0 0 IB13 0 0 0 0 0 0 IB12 0 0 0 0 0 0 IB11 0 0 0 0 0 0 IB10 0 0 0 0 0 0 IB9 0 0 0 0 0 0 IB8 0 0 0 0 0 0 IB7 0 0 0 0 VCMS EL 0 IB6 0 0 0 0 0 0 IB5 0 0 0 0 0 0 IB4 0 0 IB3 UID [3] 0 IB2 UID [2] 0 IB1 UID [1] 0 IB0 UID [0] 0
Default R29 W 1
VCM1 VCM1 VCM1 VCM1 VCM1 [4] [3] [2] [1] [0] 0 0 0 0 0
Default R2A W 1
VCM2 VCM2 VCM2 VCM2 VCM2 [4] [3] [2] [1] [0] 0 0 0 0 0
Default
UID[3:0]: The data bits UID[3:0] are written to the designated address in NVM and the written data can be read out from NVM by instruction setting (CALB) to this register. UID[3:0] can be used to write and read user identification code in NVM. The setting value in UID[3:0] bits is enabled when not reading out the setting value from NVM via CALB setting. VCM1[4:0]: Selects the factor of VREG1OUT to generate VCOMH. When enabling the setting valued in VCM1[4:0], make sure to set VCMSEL = 0. When using the data written in NVM for setting the VCOMH level, the data bits VCM1[4:0] are written to the designated address in NVM and the written data can be read out from NVM by instruction setting (CALB) to this register. When the data bits VCM2[4:0] are written in NVM before writing the data bits VCM1[4:0] to NVM, the VCM1[4:0] setting value written in NVM cannot be used for setting the VCOMH level. Note: When R29 register is read after setting CALB=1 (RA4h), data in IB7-5, R29h, is not always 0 and different data may be read out from different die. See NVM Read Out Sequence.
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R61505U Table 48
VCM1[4:0] 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08 5'h09 5'h0A 5'h0B 5'h0C 5'h0D 5'h0E 5'h0F VCOMH voltage VREG1OUT x 0.69 VREG1OUT x 0.70 VREG1OUT x 0.71 VREG1OUT x 0.72 VREG1OUT x 0.73 VREG1OUT x 0.74 VREG1OUT x 0.75 VREG1OUT x 0.76 VREG1OUT x 0.77 VREG1OUT x 0.78 VREG1OUT x 0.79 VREG1OUT x 0.80 VREG1OUT x 0.81 VREG1OUT x 0.82 VREG1OUT x 0.83 VREG1OUT x 0.84 VCM1[4:0] 5'h10 5'h11 5'h12 5'h13 5'h14 5'h15 5'h16 5'h17 5'h18 5'h19 5'h1A 5'h1B 5'h1C 5'h1D 5'h1E 5'h1F VCOMH voltage VREG1OUT x 0.85 VREG1OUT x 0.86 VREG1OUT x 0.87 VREG1OUT x 0.88 VREG1OUT x 0.89 VREG1OUT x 0.90 VREG1OUT x 0.91 VREG1OUT x 0.92 VREG1OUT x 0.93 VREG1OUT x 0.94 VREG1OUT x 0.95 VREG1OUT x 0.96 VREG1OUT x 0.97 VREG1OUT x 0.98 VREG1OUT x 0.99 VREG1OUT x 1.00
Notes: 1. Make sure the VCOMH level is set between 3.0V to (DDVDH-0.5)V. 2. The above setting is enabled when selecting internal electronic volume for setting the VCOMH level. VCM2[4:0]: Selects the factor of VREG1OUT to generate VCOMH. When enabling the setting valued in VCM2[4:0], make sure to set VCMSEL = 1. The function of VCM2[4:0] instruction is the same as that of VCM1[4:0]. Write the setting value in VCM2[4:0] bits and VCMSEL = 1 in the designated addresses of NVM, when reading out the setting value written in NVM for VCOMH level setting and the data is already written in the designated address of VCM1[4:0] in the NVM. The VCM2[4:0] data bits written in NVM can be read out via CALB setting for setting the VCOMH level. Note: When R2A register is read after setting CALB=1 (RA4h), data in IB6-5, R2Ah, is not always 0 and different data may be read out from different die. See NVM Read Out Sequence.
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R61505U Table 49
VCM2[4:0] 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08 5'h09 5'h0A 5'h0B 5'h0C 5'h0D 5'h0E 5'h0F VCOMH voltage VREG1OUT x 0.69 VREG1OUT x 0.70 VREG1OUT x 0.71 VREG1OUT x 0.72 VREG1OUT x 0.73 VREG1OUT x 0.74 VREG1OUT x 0.75 VREG1OUT x 0.76 VREG1OUT x 0.77 VREG1OUT x 0.78 VREG1OUT x 0.79 VREG1OUT x 0.80 VREG1OUT x 0.81 VREG1OUT x 0.82 VREG1OUT x 0.83 VREG1OUT x 0.84 VCM2[4:0] 5'h10 5'h11 5'h12 5'h13 5'h14 5'h15 5'h16 5'h17 5'h18 5'h19 5'h1A 5'h1B 5'h1C 5'h1D 5'h1E 5'h1F VCOMH voltage VREG1OUT x 0.85 VREG1OUT x 0.86 VREG1OUT x 0.87 VREG1OUT x 0.88 VREG1OUT x 0.89 VREG1OUT x 0.90 VREG1OUT x 0.91 VREG1OUT x 0.92 VREG1OUT x 0.93 VREG1OUT x 0.94 VREG1OUT x 0.95 VREG1OUT x 0.96 VREG1OUT x 0.97 VREG1OUT x 0.98 VREG1OUT x 0.99 VREG1OUT x 1.00
Notes: 1. Make sure the VCOMH level is set between 3.0V to (DDVDH-0.5)V. 2. The above setting is enabled when selecting internal electronic volume for setting the VCOMH level. VCMSEL: When VCMSEL = 0, VCM1[4:0] is selected. When VCMSEL = 1, VCM2[4:0] is selected.
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R61505U Control Control 1 ~ 14 (R30h to R3Dh)
R/W R 30 R 31 R 32 R 33 R 34 R 35 R 36 R 37 R 38 R 39 W RS 1 IB15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB12 0 0 0 0 0 0 0 0 0 0 0 0 IB11 0 0 0 0 0 0 0 0 0 0 0 0 IB10 IB9 IB8 P0KP P0KP P0KP 1[2] 1[1] 1[0] 0 0 0 P0KP P0KP P0KP 3[2] 3[1] 3[0] 0 0 0 P0KP P0KP P0KP 5[2] 5[1] 5[0] 0 0 0 0 0 0 P0FP 1[1] 0 P0FP 3[1] 0 0 P0FP 1[0] 0 P0FP 3[0] 0 IB7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB4 0 0 0 0 0 0 0 0 0 0 0 0 IB3 0 0 0 0 0 0 0 0 0 0 0 0 IB2 IB1 IB0 P0KP P0KP P0KP 0[2] 0[1] 0[0] 0 0 0 P0KP P0KP P0KP 2[2] 2[1] 2[0] 0 0 0 P0KP P0KP P0KP 4[2] 4[1] 4[0] 0 0 0 0 0 0 P0FP 0[1] 0 P0FP 2[1] 0 0 P0FP 0[0] 0 P0FP 2[0] 0
Default value
W
1
Default value
W
1
Default value
W
1
Default value
W
1
Default value
W
1
P0RP P0RP P0RP 1[2] 1[1] 1[0] 0 0 0
P0RP P0RP P0RP 0[2] 0[1] 0[0] 0 0 0
Default value
W
1
V0RP V0RP V0RP V0RP V0RP 1[4] 1[3] 1[2] 1[1] 1[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0K P0K P0K N1[2] N1[1] N1[0] 0 0 0 P0K P0K P0K N3[2] N3[1] N3[0] 0 0 0 P0K P0K P0K N5[2] N5[1] N5[0] 0 0 0
V0RP V0RP V0RP V0RP V0RP 0[4] 0[3] 0[2] 0[1] 0[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0K P0K P0K N0[2] N0[1] N0[0] 0 0 0 P0K P0K P0K N2[2] N2[1] N2[0] 0 0 0 P0K P0K P0K N4[2] N4[1] N4[0] 0 0 0
Default value
W
1
Default value
W
1
Default value
W
1
Default value
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R61505U Control 1 ~ 14 (R30h to R3Dh) (continued)
R/W R 3A R 3B R 3C R 3D W RS 1 IB15 0 0 0 0 0 0 0 0 IB14 0 0 0 0 0 0 0 0 IB13 0 0 0 0 0 0 0 0 IB12 0 0 0 0 0 0 IB11 0 0 0 0 0 0 IB10 0 0 0 0 IB9 IB8 P0FN P0FN 1[1] 1[0] 0 0 P0FN P0FN 3[1] 3[0] 0 0 IB7 0 0 0 0 0 0 0 0 IB6 0 0 0 0 0 0 0 0 IB5 0 0 0 0 0 0 0 0 IB4 0 0 0 0 0 0 IB3 0 0 0 0 0 0 IB2 0 0 0 0 IB1 IB0 P0FN P0FN 0[1] 0[0] 0 0 P0FN P0FN 2[1] 2[0] 0 0
Default value
W
1
Default value
W
1
P0RN P0RN P0RN 1[2] 1[1] 1[0] 0 0 0
P0RN P0RN P0RN 0[2] 0[1] 0[0] 0 0 0
Default value
W
1
V0R V0R V0R V0R V0R N1[4] N1[3] N1[2] N1[1] N1[0] 0 0 0 0 0
V0R V0R V0R V0R V0R N0[4] N0[3] N0[2] N0[1] N0[0] 0 0 0 0 0
Default value
P0KP5-0[2:0]: P0FP3-0[1:0]: P0RP1-0[2:0]: V0RP1-0[4:0]: P0KN5-0[2:0]: P0FN3-0[1:0]: P0RN1-0[2:0]: V0RN1-0[4:0]:
fine-adjustment register for positive polarity fine-adjustment register for positive polarity gradient-adjustment register for positive polarity amplitude-adjustment register for positive polarity fine-adjustment register for negative polarity fine-adjustment register for negative polarity gradient-adjustment register for negative polarity amplitude-adjustment register for negative polarity
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R61505U Window address control instruction Window Horizontal RAM Address Start/End (R50h/ R51h) Window Vertical RAM Address Start/End (R52h/R53h)
R/W R 50 R 51 R 52 R 53 W RS 1 IB15 0 0 0 0 0 0 0 0 IB14 0 0 0 0 0 0 0 0 IB13 0 0 0 0 0 0 0 0 IB12 0 0 0 0 0 0 0 0 IB11 0 0 0 0 0 0 0 0 IB10 0 0 0 0 0 0 0 0 IB9 0 0 0 0 0 0 0 0 IB8 0 0 0 0 VSA [8] 0 VEA [8] 1 IB7 HSA [7] 0 HEA [7] 1 VSA [7] 0 VEA [7] 0 IB6 HSA [6] 0 HEA [6] 1 VSA [6] 0 VEA [6] 0 IB5 HSA [5] 0 HEA [5] 1 VSA [5] 0 VEA [5] 1 IB4 HSA [4] 0 HEA [4] 0 VSA [4] 0 VEA [4] 1 IB3 HSA [3] 0 HEA [3] 1 VSA [3] 0 VEA [3] 1 IB2 HSA [2] 0 HEA [2] 1 VSA [2] 0 VEA [2] 1 IB1 HSA [1] 0 HEA [1] 1 VSA [1] 0 VEA [1] 1 IB0 HSA [0] 0 HEA [0] 1 VSA [0] 0 VEA [0] 1
Default value
W
1
Default value
W
1
Default value
W
1
Default value
HSA[7:0], HEA[7:0]: HSA[7:0] and HEA[7:0] are the start and end addresses of the window address area in horizontal direction, respectively. HSA[7:0] and HEA[7:0] specify the horizontal range to write data. Set HSA[7:0] and HEA[7:0] before starting RAM write operation. In setting, make sure that 8'h00 HSA < HEA 8'hEF and 8'h04 HEA - HSA. VSA[8:0], VEA[8:0]: VSA[8:0] and VEA[8:0] are the start and end addresses of the window address area in vertical direction, respectively. VSA[8:0] and VEA[8:0] specify the vertical range to write data. Set VSA[8:0] and VEA[8:0] before starting RAM write operation. In setting, make sure that 9'h000 VSA < VEA 9'h13F.
17'h000-00
HSA VSA HEA
Window address area setting range: 8'h00 HSA< HEA 8'hEF, HEA - HSA 8'h04, 9'h000 VSA < VEA 9'h13F
Window address area
Notes: 1. Make window address area within the GRAM address area. 2. In high-speed write mode, the R61505 writes data to the internal GRAM line by line horizontally. When writing data to the GRAM, transfer the data to be written in one line at a time.
VEA
3. Set an address within the window address area in RAM address set register (R20h, R21h). When using hight-speed write function, set an address at the start of a line.
17'h13F-EF
Figure 7 GRAM Address Map and Window Address Area
Rev.1.21 April 9, 2007, page 78 of 205
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R61505U Base image display control instruction Driver Output Control (R60h), Base Image Display Control (R61h) Vertical Scroll Control (R6Ah)
R/W R 60 R 61 R 6A W RS 1 IB15 GS 0 0 0 0 0 IB14 0 0 0 0 0 0 IB13 NL [5] 0 0 0 0 0 IB12 NL [4] 0 0 0 0 0 IB11 NL [3] 0 0 0 0 0 IB10 NL [2] 0 0 0 0 0 IB9 NL [1] 0 0 0 0 0 IB8 NL [0] 0 0 0 VL [8] 0 IB7 0 0 0 0 VL [7] 0 IB6 0 0 0 0 VL [6] 0 IB5 SCN [5] 0 0 0 VL [5] 0 IB4 SCN [4] 0 0 0 VL [4] 0 IB3 SCN [3] 0 0 0 VL [3] 0 IB2 SCN [2] 0 NDL 0 VL [2] 0 IB1 SCN [1] 0 VLE 0 VL [1] 0 IB0 SCN [0] 0 REV 0 VL [0] 0
Default value
W
1
Default value
W
1
Default value
SCN[5:0]: Specifies the gate line where the gate driver starts scan. NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping is not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel. GS: Sets the direction of scan by the gate driver. Set GS bit in combination with SM and SS bits for the convenience of the display module configuration and the display direction. REV: Enables the grayscale inversion of the image by setting REV = 1. This enables the R61505U to display the same image from the same set of data whether the liquid crystal panel is normally black or white. The source output level during front, back porch periods and blank periods is determined by register setting (PTS). Table 50 GRAM Data-grayscale level inversion
REV GRAM Data 18'h00000 0 : 18'h3FFFFF 18'h00000 1 : 18'h3FFFFF Source Output Level in Display Area Positive Polarity V31 : V0 V0 : V31 Negative Polarity V0 : V31 V31 : V0
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R61505U VLE: Vertical scroll display enable bit. When VLE = 1, the R61505U starts displaying the base image from the line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling, which is the number of lines to shift the start line of the display from the first line of the physical display. Note that the partial image display position is not affected by the base image scrolling. The vertical scrolling is not available in external display interface operation. In this case, make sure to set VLE = "0". Table 51
VLE 0 1 Base image Fixed Enable scrolling
NDL: Sets the source output level in non-lit display area. NDL bit can keep the non-display area lit on. Table 52
NDL 0 1 Non-display area Positive V31 V0 Negative V0 V31
VL[8:0]: Sets the amount of scrolling of the base image. The base image is scrolled in vertical direction and displayed from the line which is determined by VL[8:0]. Make sure VL[8:0] 320. Table 53
NL[5:0] 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D Number of Lines Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited NL[5:0] 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B Number of Lines Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited 176 lines Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited NL[5:0] 6'h1C 6'h1D 6'h1E 6'h1F 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28-6'h3F Number of Lines Setting inhibited 240 (lines) 248 256 264 272 280 288 296 304 312 320 Setting inhibited
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R61505U Table 54
Gate Line No (Scan start position) SCN[5:0] SM=0 GS=0 GS=1 SM=1 GS=0 GS=1 See note.
6'h00 G1 G320 G1 G320 6'h01 G9 G312 G17 G304 6'h02 G17 G304 G33 G288 6'h03 G25 G296 G49 G272 6'h04 G33 G288 G65 G256 6'h05 G41 G280 G81 G240 6'h06 G49 G272 G97 G224 6'h07 G57 G264 G113 G208 6'h08 G65 G256 G129 G192 6'h09 G73 G248 G145 G176 6'h0A G81 G240 G161 G160 6'h0B G89 G232 G177 G144 6'h0C G97 G224 G193 G128 6'h0D G105 G216 G209 G112 6'h0E G113 G208 G225 G96 6'h0F G121 G200 G241 G80 6'h10 G129 G192 G257 G64 6'h11 G137 G184 G273 G48 6'h12 G145 G176 G289 G32 6'h13 G153 G168 G305 G16 6'h14 G161 G160 G2 G319 6'h15 G169 G152 G18 G303 6'h16 G177 G144 G34 G287 6'h17 G185 G136 G50 G271 6'h18 G193 G128 G66 G255 6'h19 G201 G120 G82 G239 6'h1A G209 G112 G98 G223 6'h1B G217 G104 G114 G207 6'h1C G225 G96 G130 G191 6'h1D G233 G88 G146 G175 6'h1E G241 G80 G162 G159 6'h1F G249 G72 G178 G143 6'h20 G257 G64 G194 G127 6'h21 G265 G56 G210 G111 6'h22 G273 G48 G226 G95 6'h23 G281 G40 G242 G79 6'h24 G289 G32 G258 G63 6'h25 G297 G24 G274 G47 6'h26 G305 G16 G290 G31 6'h27 G313 G8 G306 G15 Setting disabled Setting disabled Setting disabled Setting disabled 6'h28-6'h3F Note: Make sure that number of scan start position + number of scan end position is 320 lines or less.
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R61505U Partial display control instruction Partial Image 1: Display Position (R80h), RAM Address (Start/End Line Address) (R81h/R82h) Partial Image 2: Display Position (R83h), RAM Address (Start/End Line Address) (R84h/R85h)
R/W R 80 R 81 R 82 W RS 1 IB15 0 0 0 0 0 0 IB14 0 0 0 0 0 0 IB13 0 0 0 0 0 0 IB12 0 0 0 0 0 0 IB11 0 0 0 0 0 0 IB10 0 0 0 0 0 0 IB9 0 0 0 0 0 0 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP 0[8] 0[7] 0[6] 0[5] 0[4] 0[3] 0[2] 0[1] 0[0] 0 0 0 0 0 0 0 0 0 PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA 0[8] 0[7] 0[6] 0[5] 0[4] 0[3] 0[2] 0[1] 0[0] 0 0 0 0 0 0 0 0 0 PTE PTE PTE PTE PTE PTE PTE PTE PTE A0[8] A0[7] A0[6] A0[5] A0[4] A0[3] A0[2] A0[1] A0[0] 0 0 0 0 0 0 0 0 0
Default value
W
1
Default value
W
1
Default value
R 83 R 84 R 85
W
1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP 1[8] 1[7] 1[6] 1[5] 1[4] 1[3] 1[2] 1[1] 1[0] 0 0 0 0 0 0 0 0 0 PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA 1[8] 1[7] 1[6] 1[5] 1[4] 1[3] 1[2] 1[1] 1[0] 0 0 0 0 0 0 0 0 0 PTE PTE PTE PTE PTE PTE PTE PTE PTE A1[8] A1[7] A1[6] A1[5] A1[4] A1[3] A1[2] A1[1] A1[0] 0 0 0 0 0 0 0 0 0
Default value
W
1
Default value
W
1
Default value
PTDP0[8:0]: Sets the display position of partial image 1. PTDP1[8:0]: Sets the display position of partial image 2. The display areas of the partial images 1 and 2 must not overlap each another. In setting, make sure that Partial image 1 display area < Partial image 2 display area, and Coordinates of partial image 1 display position: (PTDP0, PTDP0 + (PTEA0 - PTSA0)) Coordinates of partial image 2 display position: (PTDP1, PTDP1 + (PTEA1 - PTSA1)) If PTDP0 = "9'h000", the partial image 1 is displayed from the first line of the base image. PTSA0[8:0] and PTEA0[8:0]: Sets the start line and end line addresses of the RAM area, respectively for the partial image 1. In setting, make sure that PTSA0 PTEA0. PTSA1[8:0] and PTEA1[8:0]: Sets the start line and end line addresses of the RAM area, respectively for the partial image 2. In setting, make sure that PTSA1 PTEA1.
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R61505U Panel interface control instruction Panel interface control 1(R90h)
R/W W RS 1 IB15 IB14 0 0 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 DIVI [1] 0 IB8 DIVI [0] 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 IB3 IB2 IB1 IB0 RTNI RTNI RTNI RTNI RTNI [4] [3] [2] [1] [0] 1 0 0 0 0
Default value
RTNI[4:0]: Sets 1H (line) period. This setting is enabled while the R61505U's display operation is synchronized with internal clock. Table 55 Clocks per line (internal clock operation: 1 clock = 1 OSC)
RTNI[4:0] 5'h10 5'h11 5'h12 5'h13 5'h14 Clocks per Line 16 clocks 17 clocks 18 clocks 19 clocks 20 clocks RTNI[4:0] 5'h15 5'h16 5'h17 5'h18 5'h19 5'h1A Clocks per Line 21 clocks 22 clocks 23 clocks 24 clocks 25 clocks 26 clocks RTNI[4:0] 5'h1B 5'h1C 5'h1D 5'h1E 5'h1F Clocks per Line 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks 5'h00-5'h0F Setting inhibited
Note: In Power Supply Instruction Setting, Deep Standby Exit Sequence and Sleep Mode Exit Sequence, RTNI bit must be set at the "Initial instruction setting" stage. See Power supply Instruction Setting and Deep standby mode IN/EXIT sequences for detail of the timing to set the bit. DIVI[1:0]: Sets the division ratio of the internal clock frequency. The R61505U's internal operation is synchronized with the frequency divided internal clock. When DIVI[1:0] setting is changed, the width of the reference clock for liquid crystal panel control signals is changed. The frame frequency can be adjusted by register setting (RTNI and DIVI bits). When changing the number of lines to drive the liquid crystal panel, adjust the frame frequency too. For details, see "FrameFrequency Adjustment Function". The setting in DIVI[1:0] is disabled in RGB interface operation. Setting DIVI 2'h0 is inhibited. Table 56 Division ratio of the internal clock
DIVI[1:0] 2'h0 2'h1 2'h2 2'h3 Division Ratio 1/1 1/2 1/4 1/8 Internal operation clock unit 1 OSC 2 OSC 4 OSC 8 OSC
Note: In Power Supply Instruction Setting, Deep Standby Exit Sequence and Sleep Mode Exit Sequence, DIVI bit must be set at the "Initial instruction setting" stage. See Power supply Instruction Setting and Deep standby mode IN/EXIT sequences for detail of the timing to set the bit.
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R61505U Frame Frequency Calculation
Frame frequency = fosc Clocks per line x division ratio x (line + BP + FP) [Hz]
fosc : RC oscillation frequency Line: Number of lines to drive the LCD (NL bits) Division ratio: DIVI Clocks per line: RTNI
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R61505U Panel interface control 2(R92h)
R/W W RS 1 IB15 IB14 0 0 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 IB9 IB8 NOW NOW NOW I[2] I[1] I[0] 0 0 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 0 0 IB2 0 0 IB1 0 0 IB0 0 0
Default value
NOWI[2:0]: Sets the non-overlap period of adjacent gate outputs. The setting is enabled in display operation synchronizing with the internal clock. Table 57
NOWI[2:0] 3'h0 3'h1 3'h2 3'h3 Note: Non-overlap period 0 (internal clock 1 2 3
*see note
NOWI[2:0] ) 3'h4 3'h5 3'h6 3'h7
Non-overlap period 4 (internal clock 5 6 7
*see note
)
The internal clock is the frequency divided clock, which is set by DIVI[[1:0] bits.
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R61505U Panel interface control 3(R93h)
R/W W RS 1 IB15 IB14 0 0 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 VEQ WI [2] 0 IB9 VEQ WI [1] 0 IB8 VEQ WI [0] 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 0 0 IB2 MCP I[2] 0 IB1 MCP I[1] 0 IB0 MCP I[0] 0
Default value
MCPI[2:0]: Sets the source output timing by the number of internal clock from the reference point. The setting is enabled in display operation synchronizing with the internal clock. Table 58
MCPI[2:0] 3'h0 3'h1 3'h2 3'h3 Note: Source output position 0 (internal clock 1 2 3
*see note
MCPI[2:0] 3'h4 3'h5 3'h6 3'h7
Source output position 4 (internal clock) 5 6 7
)
The internal clock is the frequency divided clock, which is set by DIVI[[1:0] bits. The source output position is measured from the reference point by the number of internal clock cycle.
VEQWI [2:0]: VEQWI sets VCOM equalize period. This setting is enabled when VEM[0]=(R0Eh) and display operation of the R61505U is synchronized with internal clock. VEQWI setting is enabled when RGB interface is selected. Table 59
VEQWI[2:0] VCOM equalize period 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 0 clocks 1 clock 2 clocks 3 clocks 4 clocks Setting disabled Setting disabled Setting disabled
Note: DIVI (R90h) sets division ratio of clock frequency.
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R61505U Panel interface control 4(R95h)
R/W W RS 1 IB15 IB14 0 0 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 IB8 DIVE DIVE [1] [0] 1 0 IB7 0 0 IB6 0 0 IB5 RTN E[5] 0 IB4 RTN E[4] 1 IB3 RTN E[3] 1 IB2 RTN E[2] 1 IB1 RTN E[1] 1 IB0 RTN E[0] 0
Default value
RTNE[5:0]: Sets RTNE[5:0] and DIVE[1:0] bits so that the number of DOTCLK calculated from the following formula becomes the number of DOTCLK which should be inputted in 1H period. The RTNE[5:0] setting is enabled in display operation via RGB interface. DIVE[1:0] (division ratio) x RTNE[5:0] (Number of DOTCLK) Number of DOTCLK in 1H period DIVE[1:0]: Sets the division ratio of DOTCLK frequency. The R61505U's internal operation is synchronized with the frequency divided DOTCLK. The setting in DIVE[1:0] is enabled in RGB interface operation. Table 60 Division ratio of DOTCLK
DIVE[1:0] 2'h0 2'h1 2'h2 2'h3 Division Ratio Internal operation clock unit (DOTCLK)
18-bit, 1 transfer RGB interface DOTCLK = 5 MHz 6-bit, 3 transfers RGB interface DOTCLK = 15 MHz
Setting disabled Setting disabled
0.8s 1.6s 3.2s
Setting disabled
0.8s 1.6s 3.2s
1/4 1/8 1/16
4 DOTCLKs 8 DOTCLKs 16 DOTCLKs
12 DOTCLKs 24 DOTCLKs 48 DOTCLKs
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R61505U Table 61 DOTCLK per line (1H period)
RTNE[5:0] 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F DOTCLK per line (1H) Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled 16 clocks 17 clocks 18 clocks 19 clocks 20 clocks 21 clocks 22 clocks 23 clocks 24 clocks 25 clocks 26 clocks 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks RTNE[5:0] 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 6'h29 6'h2A 6'h2B 6'h2C 6'h2D 6'h2E 6'h2F 6'h30 6'h31 6'h32 6'h33 6'h34 6'h35 6'h36 6'h37 6'h38 6'h39 6'h3A 6'h3B 6'h3C 6'h3D 6'h3E 6'h3F DOTCLK per line (1H) 32 clocks 33 clocks 34 clocks 35 clocks 36 clocks 37 clocks 38 clocks 39 clocks 40 clocks 41 clocks 42 clocks 43 clocks 44 clocks 45 clocks 46 clocks 47 clocks 48 clocks 49 clocks 50 clocks 51 clocks 52 clocks 53 clocks 54 clocks 55 clocks 56 clocks 57 clocks 58 clocks 59 clocks 60 clocks 61 clocks 62 clocks 63 clocks
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R61505U Panel interface control 5(R97h)
R/W W RS 1 IB15 IB14 0 0 0 0 IB13 0 0 IB12 0 0 IB11 IB10 IB9 IB8 NOW NOW NOW NOW E[3] E[2] E[1] E[0] 0 0 0 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 0 0 IB2 0 0 IB1 0 0 IB0 0 0
Default value
NOWE[3:0]: Sets the non-overlap period of adjacent gate outputs. The setting is enabled in display operation via RGB interface. Table 62
NOWE[3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 Note: Non-overlap period 0 (clock 1 2 3 4 5 6 7
*see note
NOWE[3:0] 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF
Non-overlap period 8 (clocks 9 10 11 12 13 14 15
*see note)
)
1 clock = (Number of data transfers/pixel) x DIVE (division ratio) [DOTCLK].
Panel interface control 6(R98h)
R/W W RS 1 IB15 IB14 0 0 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 0 0 IB8 0 0 IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 0 0 IB2 MCP E[2] 0 IB1 MCP E[1] 0 IB0 MCP E[0] 0
Default value
MCPE[2:0]: Sets the source output timing by the number of internal clock from the reference point. The setting is enabled in display operation via RGB interface. Table 63
MCPE[2:0] 3'h0 3'h1 3'h2 3'h3 Note: Source output position Setting Disabled 1 clock 2 3 MCPE[2:0] 3'h4 3'h5 3'h6 3'h7 Source output position 4 (clocks 5 6 7
*see note
)
1 clock = (Number of data transfers/pixel) x DIVE (division ratio) [DOTCLK].
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R61505U NVM(NON-VOLATILE MEMORY) control NVM access control 1 (RA0h), NVM access control 2 (RA1h)
R/W RA0 W RS 1 IB15 0 0 0 0 IB14 0 0 0 0 IB13 0 0 0 0 IB12 0 0 0 0 IB11 0 0 0 0 IB10 0 0 0 0 IB9 0 0 0 0 IB8 0 0 0 0 IB7 TE 0 ED [7] 0 IB6 0 0 0 0 IB5 EOP [1] 0 0 0 IB4 EOP [0] 0 ED [4] 0 IB3 0 0 ED [3] 0 IB2 0 0 ED [2] 0 IB1 EAD [1] 0 ED [1] 0 IB0 EAD [0] 0 ED [0] 0
Default RA1 W Default
EAD[1:0]: Designates the address in NVM, where the data is written. See also description of ED7 and ED4-0 bits below. Table 64
EAD[1:0] 2'h0 2'h1 2'h2 2'h3 Data written in NVM UID[3:0] VCM1[4:0] VCMSEL, VCM2[4:0] Setting disabled
EOP [1:0]: Internal NVM control bits to write-in data to NVM, and halt write-in operation. Table 65
EOP[1:0] 2'h0 2'h1 2'h2 2'h3 NVM control Halt Write Setting disabled Setting disabled
TE: Enable internal NVM control bit (EOP). Follow the NVM control sequence when setting TE. ED [7], [4:0]: The data written in the Internal NVM. Table 66
EAD[1:0] 2'h0 2'h1 2'h2 ED7 0 0 VCMSEL ED6 0 0 0 ED5 0 0 0 ED4 0 VCM1[4] VCM2[4] ED3 UID[3] VCM1[3] VCM2[3] ED2 UID[2] VCM1[2] VCM2[2] ED1 UID[1] VCM1[1] VCM2[1] ED0 UID[0] VCM1[0] VCM2[0]
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R61505U Calibration control (RA4h)
R/W RS W
Default Value
IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IB8 0 0
IB7 0 0
IB6 0 0
IB5 0 0
IB4 0 0
IB3 0 0
IB2 0 0
IB1 0 0
IB0
CALB
1
0
CALB: Instruction to read in data on NVM. When CALB=1, data written to NVM is read out to internal register. CALB sets oscillation frequency at 376kHz +/- 7% (R61505U0) or 600kHz +/- 7% (R61505U1). (IOVCC=VCC=3V, 25C). Make sure to input CALB=1 every time after power on reset. Inputting CALB=1 periodically is highly recommended to reduce erroneous display operation caused by noise from outside of the R61505U.
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R61505U Setting disabled instruction (Inhibition) Setting is inhibited for the registers listed as follows. DO NOT ACCESS TO THESE REGISTERS. R05h-R06h, R0Bh, R14h-R16h, R18h, R1A-R1Fh, R23h-R27h, R2Bh-R2Fh, R3Eh-R3Fh, R54h-R5Fh, R62h-R69h, R6Bh-R6Fh, R86h-R8Fh, R91h, R94h, R96h, R99h-R9Fh, RA2h-RA3h, RA5h-RAFh, RB*hRF*h
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R61505UInstruction List
Main Category
Upper Index
07,03.09 Rev1.2 Sub Category Command Index Device Code Read Driver Output Control LCD Drive Waveform Cotrol Entry Mode Resize Control Setting inhibited Display Control 1 Display Control 2 Display Control 3 Display Control 4 Setting inhibited IB15 * 0 0 0 TRIREG (0) 0 Setting inhibited 0 0 0 0 Setting inhibited 0 0 0 0 0 0 0 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited 0 0 IB14 * 0 0 0 DFM (0) 0 Setting inhibited 0 0 0 0 Setting inhibited ENC[2] (0) 0 0 0 SAP[1] (0) 0 0 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited 0 0 IB13 * 0 0 0 0 0 Setting inhibited PTDE[1] (0) 0 0 0 Setting inhibited ENC[1] (0) 0 0 0 SAP[0] (0) 0 0 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited 0 0 Upper code IB12 IB11 * * 1 0 0 BGR (0) 0 Setting inhibited PTDE[0] (0) 0 0 0 Setting inhibited ENC[0] (0) 0 0 0 SAP (0) 0 0 VDV[4] (0) Setting inhibited 0 Setting inhibited 0 Setting inhibited 0 0 0 0 0 0 0 Setting inhibited 0 FP[3] (1) 0 0 Setting inhibited 0 0 0 0 0 0 0 VDV[3] (0) Setting inhibited 0 Setting inhibited 0 Setting inhibited 0 0 IB10 * 1 SM (0) 1 (1) 0 0 Setting inhibited 0 FP[2] (0) PTS[2] (0) 0 Setting inhibited 0 0 0 0 BT[2] (0) DC1[2] (1) 0 VDV[2] (0) Setting inhibited 0 Setting inhibited 0 Setting inhibited 0 0 IB9 * 0 0 BC0 (0) HWM (0) RCV[1] (0) Setting inhibited 0 FP[1] (0) PTS[1] (0) 0 Setting inhibited 0 0 0 0 BT[1] (0) DC1[1] (1) 0 VDV[1] (0) Setting inhibited 0 Setting inhibited TBT[1] (1) Setting inhibited 0 0 IB8 * 1 SS (0) EOR (0) 0 RCV[0] (0) Setting inhibited BASEE (0) FP[0] (0) PTS[0] (0) 0 Setting inhibited RM (0) FMP[8] (0) 0 0 BT[0] (0) DC1[0] (0) VCMR[0] (0) VDV[0] (0) Setting inhibited 0 Setting inhibited TBT[0] (1) Setting inhibited 0 AD[16] (0) Setting inhibited 0 0 0 Setting inhibited P0KP1[0] (0) P0KP3[0] (0) P0KP5[0] (0) P0FP1[0] (0) P0FP3[0] (0) P0RP1[0] (0) V0RP1[0] (0) P0KN1[0] (0) P0KN3[0] (0) P0KN5[0] (0) P0FN1[0] (0) P0FN3[0] (0) P0RN1[0] (0) V0RN1[0] (0) Setting inhibited 0 0 VSA[8] (0) VEA[8] (1) Setting inhibited NL[0] (0) 0 Setting inhibited VL[8] (0) Setting inhibited PTDP0[8] (0) PTSA0[8] (0) PTEA0[8] (0) PTDP1[8] (0) PTSA1[8] (0) PTEA1[8] (0) Setting inhibited DIVI[0] (0) Setting inhibited NOWI[0] (0) VEQWI[0] Setting inhibited DIVE[0] (0) Setting inhibited NOWE[0] (0) 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited Setting inhibited IB7 ID7 0 0 0 ORG (0) 0 Setting inhibited 0 0 0 0 Setting inhibited 0 FMP[7] (0) 0 0 APE(0) 0 VREG1R (0) 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited AD[7] (0) AD[15] (0) Setting inhibited 0 0 VCMSEL (0) Setting inhibited 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited HSA[7] (0) HEA[7] (1) VSA[7] (0) VEA[7] (0) Setting inhibited 0 0 Setting inhibited VL[7] (0) Setting inhibited PTDP0[7] (0) PTSA0[7] (0) PTEA0[7] (0) PTDP1[7] (0) PTSA1[7] (0) PTEA1[7] (0) Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited TE (0) ED7 (0) Setting inhibited 0 Setting inhibited Setting inhibited IB6 ID6 0 0 0 0 0 Setting inhibited VON (0) 0 0 0 Setting inhibited 0 FMP[6] (0) 0 0 AP[2] (0) DC0[2] (1) 0 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited AD[6] (0) AD[14] (0) Setting inhibited 0 0 0 Setting inhibited 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited HSA[6] (0) HEA[6] (1) VSA[6] (0) VEA[6] (0) Setting inhibited 0 0 Setting inhibited VL[6] (0) Setting inhibited PTDP0[6] (0) PTSA0[6] (0) PTEA0[6] (0) PTDP1[6] (0) PTSA1[6] (0) PTEA1[6] (0) Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited Setting inhibited IB5 ID5 0 0 0 ID1 (1) RCH[1] (0) Setting inhibited GON (0) 0 PTG[1] (0) 0 Setting inhibited DM[1] (0) FMP[5] (0) 0 0 AP[1] (0) DC0[1] (1) PSON (0) 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited AD[5] (0) AD[13] (0) Setting inhibited 0 0 0 Setting inhibited 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited HSA[5] (0) HEA[5] (1) VSA[5] (0) VEA[5] (1) Setting inhibited SCN[5] (0) 0 Setting inhibited VL[5] (0) Setting inhibited PTDP0[5] (0) PTSA0[5] (0) PTEA0[5] (0) PTDP1[5] (0) PTSA1[5] (0) PTEA1[5] (0) Setting inhibited 0 Setting inhibited 0 0 Setting inhibited RTNE[5] (0) Setting inhibited 0 0 Setting inhibited EOP[1] (0) 0 Setting inhibited 0 Setting inhibited Setting inhibited Lower code IB4 IB3 ID4 ID3 0 0 0 ID0 (1) RCH[0] (0) Setting inhibited DTE (0) 0 PTG[0] (0) 0 Setting inhibited DM[0] (0) FMP[4] (0) VEM[0] VSPL (0) AP[0] (0) DC0[0] (0) PON (0) 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited AD[4] (0) AD[12] (0) Setting inhibited 0 VCM1[4] (0) VCM2[4] (0) Setting inhibited 0 0 0 0 0 0 V0RP0[4] (0) 0 0 0 0 0 0 V0RN0[4] (0) Setting inhibited HSA[4] (0) HEA[4] (0) VSA[4] (0) VEA[4] (1) Setting inhibited SCN[4] (0) 0 Setting inhibited VL[4] (0) Setting inhibited PTDP0[4] (0) PTSA0[4] (0) PTEA0[4] (0) PTDP1[4] (0) PTSA1[4] (0) PTEA1[4] (0) Setting inhibited RTNI[4] (1) Setting inhibited 0 0 Setting inhibited RTNE[4] (1) Setting inhibited 0 0 Setting inhibited EOP[0] (0) ED4 (0) Setting inhibited 0 Setting inhibited Setting inhibited 0 0 0 AM (0) 0 Setting inhibited COL (0) BP[3] (1) ISC[3] (0) FMARKOE (0) Setting inhibited 0 FMP[3] (0) 0 HSPL (0) 0 0 VRH[3] (0) 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited AD[3] (0) AD[11] (0) Setting inhibited UID[3] (0) VCM1[3] (0) VCM2[3] (0) Setting inhibited 0 0 0 0 0 0 V0RP0[3] (0) 0 0 0 0 0 0 V0RN0[3] (0) Setting inhibited HSA[3] (0) HEA[3] (1) VSA[3] (0) VEA[3] (1) Setting inhibited SCN[3] (0) 0 Setting inhibited VL[3] (0) Setting inhibited PTDP0[3] (0) PTSA0[3] (0) PTEA0[3] (0) PTDP1[3] (0) PTSA1[3] (0) PTEA1[3] (0) Setting inhibited RTNI[3] (0) Setting inhibited 0 0 Setting inhibited RTNE[3] (1) Setting inhibited 0 0 Setting inhibited 0 ED3 (0) Setting inhibited 0 Setting inhibited Setting inhibited IB2 ID2 1 0 0 0 0 Setting inhibited 0 BP[2] (0) ISC[2] (0) FMI[2] (0) Setting inhibited 0 FMP[2] (0) 0 0 DSTB (0) VC[2] (0) VRH[2] (0) 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited AD[2] (0) AD[10] (0) Setting inhibited UID[2] (0) VCM1[2] (0) VCM2[2] (0) Setting inhibited P0KP0[2] (0) P0KP2[2] (0) P0KP4[2] (0) 0 0 P0RP0[2] (0) V0RP0[2] (0) P0KN0[2] (0) P0KN2[2] (0) P0KN4[2] (0) 0 0 P0RN0[2] (0) V0RN0[2] (0) Setting inhibited HSA[2] (0) HEA[2] (1) VSA[2] (0) VEA[2] (1) Setting inhibited SCN[2] (0) NDL (0) Setting inhibited VL[2] (0) Setting inhibited PTDP0[2] (0) PTSA0[2] (0) PTEA0[2] (0) PTDP1[2] (0) PTSA1[2] (0) PTEA1[2] (0) Setting inhibited RTNI[2] (0) Setting inhibited 0 MCPI[2] (0) Setting inhibited RTNE[2] (1) Setting inhibited 0 MCPE[2] (0) Setting inhibited 0 ED2 (0) Setting inhibited 0 Setting inhibited Setting inhibited IB1 ID1 0 0 0 0 RSZ[1] (0) Setting inhibited D[1] (0) BP[1] (0) ISC[1] (0) FMI[1] (0) Setting inhibited RIM[1] (0) FMP[1] (0) 0 EPL (0) SLP (0) VC[1] (0) VRH[1] (0) 0 Setting inhibited 0 Setting inhibited 0 Setting inhibited AD[1] (0) AD[9] (0) Setting inhibited UID[1] (0) VCM1[1] (0) VCM2[1] (0) Setting inhibited P0KP0[1] (0) P0KP2[1] (0) P0KP4[1] (0) P0FP0[1] (0) P0FP2[1] (0) P0RP0[1] (0) V0RP0[1] (0) P0KN0[1] (0) P0KN2[1] (0) P0KN4[1] (0) P0FN0[1] (0) P0FN2[1] (0) P0RN0[1] (0) V0RN0[1] (0) Setting inhibited HSA[1] (0) HEA[1] (1) VSA[1] (0) VEA[1] (1) Setting inhibited SCN[1] (0) VLE (0) Setting inhibited VL[1] (0) Setting inhibited PTDP0[1] (0) PTSA0[1] (0) PTEA0[1] (0) PTDP1[1] (0) PTSA1[1] (0) PTEA1[1] (0) Setting inhibited RTNI[1] (0) Setting inhibited 0 MCPI[1] (0) Setting inhibited RTNE[1] (1) Setting inhibited 0 MCPE[1] (0) Setting inhibited EAD[1] (0) ED1 (0) Setting inhibited 0 Setting inhibited Setting inhibited IB0 ID0 1 0 NW0 (0) 0 RSZ[0] (0) Setting inhibited D[0] (0) BP[0] (0) ISC[0] (0) FMI[0] (0) Setting inhibited RIM[0] (0) FMP[0] (0) 0 DPL (0) 0 VC[0] (0) VRH[0] (0) 0 Setting inhibited PSE (0) Setting inhibited 0 Setting inhibited AD[0] (0) AD[8] (0) Setting inhibited UID[0] (0) VCM1[0] (0) VCM2[0] (0) Setting inhibited P0KP0[0] (0) P0KP2[0] (0) P0KP4[0] (0) P0FP0[0] (0) P0FP2[0] (0) P0RP0[0] (0) V0RP0[0] (0) P0KN0[0] (0) P0KN2[0] (0) P0KN4[0] (0) P0FN0[0] (0) P0FN2[0] (0) P0RN0[0] (0) V0RN0[0] (0) Setting inhibited HSA[0] (0) HEA[0] (1) VSA[0] (0) VEA[0] (1) Setting inhibited SCN[0] (0) REV (0) Setting inhibited VL[0] (0) Setting inhibited PTDP0[0] (0) PTSA0[0] (0) PTEA0[0] (0) PTDP1[0] (0) PTSA1[0] (0) PTEA1[0] (0) Setting inhibited RTNI[0] (0) Setting inhibited 0 MCPI[0] (0) Setting inhibited RTNE[0] (0) Setting inhibited 0 MCPE[0] (0) Setting inhibited EAD[0] (0) ED0 (0) Setting inhibited CALB (0) Setting inhibited Setting inhibited Notes
-
Index
Index 00h 01h 02h 03h 04h 05h-06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
Device Code "1505"
External Display Interface Control 1 Frame Marker Control VCOM Low Power Control External Display Interface Control 2 Power Control 1 Power Control 2 Power Control 3 Power Control 4 Setting inhibited Power Control 5 Setting inhibited Power Control 6 Setting inhibited RAM Adddress Set (Horizontal) RAM Adddress Set (Vertical) Write Data to / Read Data from GRAM Setting inhibited NVM Data Read VCOM High Voltage VCOM High Voltage Setting inhibited Gamma Control 1 Gamma Control 2 Gamma Control 3 Gamma Control 4 Gamma Control 5 Gamma Control 6 Gamma Control 7 Gamma Control 8 Gamma Control 7 Gamma Control 7 Gamma Control 11 Gamma Control 12 Gamma Control 13 Gamma Control 14 Setting inhibited Window Horizontal RAM Address (Start Addres Window Horizontal RAM Address (End Address Window Vertical RAM Address (Start Address Window Vertical RAM Address (End Address) Setting inhibited Driver Output Control Base Image Display Control Setting inhibited Vertical Scroll Control Setting inhibited Partial Image 1 Display Position Partial Image 1 RAM Address (Start Line Address) Partial Image 1 RAM Address (End Line Address) Partial Image 2 Display Position Partial Image 2 RAM Address (Start Line Address) Partial Image 2 RAM Address (End Line Address) Setting inhibited Panel Interface Control 1 Setting inhibited Panel Interface Control 2 Panel Interface Control 3 Setting inhibited Panel Interface Control 4 Setting inhibited Panel Interface Control 5 Panel Interface Control 6 Setting inhibited NVM Access Control 1 NVM Access Control 2 Setting inhibited Calibration Control Setting inhibited Setting inhibited
1*
Power Control
10h 11h 12h 13h 14h-16h 17h 18h 19h 1Ah-1Fh
2*
RAM Access
20h 21h 22h 23h-27h 28h 29h 2Ah 2Bh-2Fh
RAM write data (WD17-0) / RAM read data (RD17-0) bits are allocated to different data bus according to the format of selected interface.
Setting inhibited 0 0 0 Setting inhibited 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited 0 0 0 0 Setting inhibited GS (0) 0 Setting inhibited 0 Setting inhibited 0 0 0 0 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited Setting inhibited Setting inhibited 0 0 0 Setting inhibited 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited 0 0 0 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited 0 0 0 0 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited Setting inhibited Setting inhibited 0 0 0 Setting inhibited 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited 0 0 0 0 Setting inhibited NL[5] (0) 0 Setting inhibited 0 Setting inhibited 0 0 0 0 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited Setting inhibited Setting inhibited 0 0 0 Setting inhibited 0 0 0 0 0 0 V0RP1[4] (0) 0 0 0 0 0 0 V0RN1[4] (0) Setting inhibited 0 0 0 0 Setting inhibited NL[4] (0) 0 Setting inhibited 0 Setting inhibited 0 0 0 0 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited Setting inhibited Setting inhibited 0 0 0 Setting inhibited 0 0 0 0 0 0 V0RP1[3] (0) 0 0 0 0 0 0 V0RN1[3] (0) Setting inhibited 0 0 0 0 Setting inhibited NL[3] (0) 0 Setting inhibited 0 Setting inhibited 0 0 0 0 0 0 Setting inhibited 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited NOWE[3] (0) 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited Setting inhibited Setting inhibited 0 0 0 Setting inhibited P0KP1[2] (0) P0KP3[2] (0) P0KP5[2] (0) 0 0 P0RP1[2] (0) V0RP1[2] (0) P0KN1[2] (0) P0KN3[2] (0) P0KN5[2] (0) 0 0 P0RN1[2] (0) V0RN1[2] (0) Setting inhibited 0 0 0 0 Setting inhibited NL[2] (0) 0 Setting inhibited 0 Setting inhibited 0 0 0 0 0 0 Setting inhibited 0 Setting inhibited NOWI[2] (0) VEQWI[2] Setting inhibited 0 Setting inhibited NOWE[2] (0) 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited Setting inhibited Setting inhibited 0 0 0 Setting inhibited P0KP1[1] (0) P0KP3[1] (0) P0KP5[1] (0) P0FP1[1] (0) P0FP3[1] (0) P0RP1[1] (0) V0RP1[1] (0) P0KN1[1] (0) P0KN3[1] (0) P0KN5[1] (0) P0FN1[1] (0) P0FN3[1] (0) P0RN1[1] (0) V0RN1[1] (0) Setting inhibited 0 0 0 0 Setting inhibited NL[1] (0) 0 Setting inhibited 0 Setting inhibited 0 0 0 0 0 0 Setting inhibited DIVI[1] (0) Setting inhibited NOWI[1] (0) VEQWI[1] Setting inhibited DIVE[1] (1) Setting inhibited NOWE[1] (0) 0 Setting inhibited 0 0 Setting inhibited 0 Setting inhibited Setting inhibited
3*
Gamma Control
30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh-3Fh
5*
Coordinates Control
50h 51h 52h 53h 54h-5Fh
6*
Panel Image Control
60h 61h 62h-69h 6Ah 6Bh-6Fh
8*
Partial Image Control
80h 81h 82h 83h 84h 85h 86h-8Fh
9*
Panel Interface Control
90h 91h 92h 93h 94h 95h 96h 97h 98h 99h-9Fh
A*
NVM Control
A0h A1h A2h-A3h A4h A5h-AFh
B*-F*
Setting inhibited
B*h-F*h
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R61505U
Reset Function
The R61505U is initialized by the RESET input. During reset period, the R61505U is in a busy state and instruction from the microcomputer and GRAM access are not accepted. The R61505U's internal power supply circuit unit is initialized also by the RESET input. The RESET period must be secured for at least 1ms. In case of power-on reset, wait until the RC oscillation frequency stabilizes (for 1 ms). During this period, GRAM access and initial instruction setting are prohibited. 1. Initial state of instruction bits (default)
See the instruction list of p.93. The default value is shown in the parenthesis of each instruction bit cell. 2. RAM Data initialization
The RAM data is not automatically initialized by the RESET input. It must be initialized by software in display-off period (D1-0 = "00"). 3. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 4. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Output pin initial state * see Note LCD driver S1~S720 G1~G320 VCOM VCOMH VCOML VREG1OUT VCIOUT VLOUT1 (DDVDH) VLOUT2 (VGH) VLOUT3 (VGL) VCL VCI1 FMARK SDO : GND : VGL (= GND) : Halt (GND output) : DDVDH : Halt (GND output) : VGS : Hi-z : VCI clamp : DDVDH clamp : GND : GND : Hi-z : Halt (GND output ) : High level (IOVCC) when IM = "010*"(serial interface) : Hi-z when IM "010*"(other than serial interface) : Hi-z : Hi-z : Hi-z : Hi-z : VCI1 (= Hi-z) : GND : DDVDH : GND : DDVDH : GND : DDVDH : GND : VDD
Initial state of input/output pins* see Note C11+ C11C12+ C12C13+ C13C21+ C21C22+ C22C23+ C23VDD
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R61505U Note: The above mentioned initial states of output and input pins are those of when the R61505U's power supply circuit is connected as exemplified in "Connection example".
5.
Note on Reset function (1) When RESET is inputted into the R61505U while it is in deep standby mode, the R61505U starts up the inside logic regulator and makes a transition to the initial state. During this period, the state of the interface pins may become unstable. For this reason, do not enter a RESET input in deep standby mode. (2) When transferring instruction in either two or three transfers via 8-/9-/16-bit interface, make sure to execute data transfer synchronization after reset operation.
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R61505U
Basic mode operation of the R61505U
The basic operation modes of the R61505U are shown in the following diagram. When making a transition from one mode to another, refer to instruction setting sequence.
Sleep mode
Sleep set
Exit Sleep
Display OFF
Initial setting DSTB = 1 Deep standby set
Reset state
Reset
Exit deep standby Deep standby mode RAM access via system i/F while displaying moving picture RGB i/F (2) sequence 1 (DM=01, RM=0) RGB interface (2) RGB i/F (2) sequence 2 (DM=01, RM=1)
Display OFF sequence (Power OFF sequence)
Display ON sequence (Power ON sequence)
moving picture display
VSYNC interface
VSYNC i/F sequence 2 (DM=10, RM=0) VSYNC i/F sequence 1 (DM=00, RM=0)
Internal clock display operation
RGB i/F (1) sequence 1 (DM=01, RM=1) RGB i/F (1) sequence 2 (DM=00, RM=0)
moving picture display RGB interface (1)
Partial display sequence 2
Partial display sequence 1
Partial display
Display color control
262k-color mode
8 262k color display sequence
262k 8 color display sequence
8-color mode
Figure 8
Rev.1.21 April 9, 2007, page 96 of 205
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R61505U
Interface and data format
The R61505U supports system interface for making instruction and other settings, and external display interface for displaying a moving picture. The R61505U can select the optimum interface for the display (moving or still picture) in order to transfer data efficiently. As external display interface, the R61505U supports RGB interface and VSYNC interface, which enables data rewrite operation without flickering the moving picture on display. In RGB interface operation, the display operation is executed in synchronization with synchronous signals VSYNC, HSYNC, and DOTCLK. In synchronization with these signals, the R61505U writes display data according to data enable signal (ENABLE) via RGB data signal bus (DB17-0). The display data is stored in the R61505U's GRAM so that data is transferred only when rewriting the frames of moving picture and the data transfer required for moving picture display can be minimized. The window address function specifies the RAM area to write data for moving picture display, which enables displaying a moving picture and RAM data in other than the moving picture area simultaneously. To access the R61505U's internal RAM in high speed with low power consumption, use high-speed write function (HWM = 1) in RGB or VSYNC interface operation. In VSYNC interface operation, the internal display operation is synchronized with the frame synchronization signal (VSYNC). The VSYNC interface enables a moving picture display via system interface by writing the data to the GRAM at faster than the minimum calculated speed in synchronization with the falling edge of VSYNC. In this case, there are restrictions in setting the frequency and the method to write data to the internal RAM. The R61505U operates in either one of the following four modes according to the state of the display. The operation mode is set in the external display interface control register (R0Ch). When switching from one mode to another, make sure to follow the relevant sequence in setting instruction bits. Table 67 Operation Modes
Operation Mode Internal clock operation (displaying still pictures) RGB interface (1) (displaying moving pictures) RGB interface (2) (rewriting still pictures while displaying moving pictures) VSYNC interface (displaying moving pictures) RAM Access Setting (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0) Display Operation Mode (DM) Internal clock operation (DM1-0 = 00) RGB interface (DM1-0 = 01) RGB interface (DM1-0 = 01) VSYNC interface (DM1-0 = 10)
Notes:
1. 2. 3.
Instructions are set only via system interface.
The RGB and VSYNC interfaces cannot be used simultaneously. Do not make changes to the RGB interface operation setting (RIM1-0) while RGB interface is in operation. 4. See the "External Display Interface" section for the sequences when switching from one mode to another. 5. Use high-speed write function (HWM = 1) when writing data via RGB or VSYNC interface.
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R61505U
CS* System interface RS WR* (RD*) System interface 18/16/9/8
System
DB17-0 RGB interface 18/16/6
R61505U
ENABLE VSYNC HSYNC DOTCLK
RGB interface
Figure 9
Internal clock operation The display operation is synchronized with signals generated from internal oscillator's clock (OSC) in this mode. All input via external display interface is disabled in this operation. The internal RAM can be accessed only via system interface. RGB interface operation (1) The display operation is synchronized with frame synchronous signal (VSYNC), line synchronous signal (HSYNC), and dot clock signal (DOTCLK) in RGB interface operation. These signals must be supplied during the display operation via RGB interface. The R61505U transfers display data in units of pixels via DB17-0 pins. The display data is stored in the internal RAM. The combined use of high-speed RAM write mode and window address function can minimize the total number of data transfer for moving picture display by transferring only the data to be written in the moving picture RAM area when it is written and enables the R61505U to display a moving picture and the data in other than the moving picture RAM area simultaneously. The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated inside the R61505U by counting the number of clocks of line synchronous signal (HSYNC) from the falling edge of the frame synchronous signal (VSYNC). Make sure to transfer pixel data via DB17-0 pins in accordance with the setting of these periods.
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R61505U RGB interface operation (2) This mode enables the R61505U to rewrite RAM data via system interface while using RGB interface for display operation. To rewrite RAM data via system interface, make sure that display data is not transferred via RGB interface (ENABLE = high). To return to the RGB interface operation, change the ENABLE setting first. Then set an address in the RAM address set register and R22h in the index register. VSYNC interface operation The internal display operation is synchronized with the frame synchronous signal (VSYNC) in this mode. This mode enables the R61505U to display a moving picture via system interface by writing data in the internal RAM at faster than the calculated minimum speed via system interface from the falling edge of frame synchronous (VSYNC). In this case, there are restrictions in speed and method of writing RAM data. For details, see the "VSYNC Interface" section. As external input, only VSYNC signal input is valid in this mode. Other input via external display interface becomes disabled. The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated from the frame synchronous signal (VSYNC) inside the R61505U according to the instruction settings for these periods. FMARK interface operation In the FMARK interface operation, data is written to internal RAM via system interface synchronizing with the frame mark signal (FMARK), realizing tearing-less moving picture while using conventional system interface. In this case, there are restrictions in speed and method of writing RAM data. See "FMARK interface" for detail.
Rev.1.21 April 9, 2007, page 99 of 205
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R61505U
System Interface
The following are the kinds of system interfaces available with the R61505U. The interface operation is selected by setting the IM3/2/1/0 pins. The system interface is used for instruction setting and RAM access. Table 68 IM Bit Settings and System Interface
IM3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IM2 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 IM1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 IM0 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 Interfacing Mode with MPU Setting inhibited Setting inhibited 80-system 16-bit interface 80-system 8-bit interface Clock synchronous serial interface Setting inhibited Setting inhibited Setting inhibited Setting inhibited 80-system 18-bit interface 80-system 9-bit interface Setting inhibited Setting inhibited Setting inhibited Setting inhibited DB Pins DB17-10, DB8-1 DB17-10 DB17-0 DB17-9 Colors 262,144 *see Note1 262,144 *see Note2 65,536 262,144 262,144 -
Notes: 1. 65,536 colors in 16-bit single transfer mode. 2. 65,536 colors in 8-bit 2-transfer mode.
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R61505U 80-system 18-bit Bus Interface
IM[3:0] = 1010 CSn* A1 CS* RS WR* (RD*) DB17-0
MPU
HWR (RD*) D31-0
R61505U
18
Figure 10 18-bit interface
Instruction write
Input
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
Device code read
Device code
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Output
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
Instruction code
Figure 11 18-bit Interface Data Format (Instruction Write / Device Code Read)
RAM data write
Input
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
GRAM write data
R5
R4
R3
R2
R1
R0
G5
G4
G3
1 pixel
G2
G1
G0
B5
B4
B3
B2
B1
B0
Note: Normal display in 262,144 colors
RAM data read
GRAM data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Read data
RD RD [17] [16]
RD [15]
RD RD RD RD [14] [13] [12] [11]
RD [10]
RD [9]
RD [8]
RD [7]
RD [6]
RD [5]
RD [4]
RD [3]
RD [2]
RD [1]
RD [0]
Output pins
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
Figure 12 18-bit Interface Data Format (RAM Data Write / RAM Data Read)
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R61505U 80-system 16-bit Bus Interface
IM[3:0] = 0010 CSn* A1 CS* RS WR* (RD*) DB17-10, 8-1
MPU
HWR (RD*) D15-0
R61505U
16
Figure 13 16-bit interface
Instruction
Input
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
Device code read
Device code
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Output
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
Instruction code
Note: Device code cannot be read in 2 transfer mode.
Figure 14 16-bit Interface Data Format (Instruction Write / Device Code Read)
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R61505U
RAM data write (single transfer mode: TRIREG = 0)
Input
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Note: Normal display in 65,536 colors
RAM data write (2 transfer mode: TRIREG = 1, DFM =0)
First transfer
Input pins
Second transfer
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 17
DB 16
GRAM write data
WD [17]
WD [16]
WD [15]
WD [14]
WD [13]
WD [12]
WD [11]
WD [10]
WD [9]
WD [8]
WD [7]
WD [6]
WD [5]
WD [4]
WD [3]
WD [2]
WD [1]
WD [0]
RGB assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: Normal display in 262,144 colors
RAM data write (2 transfer mode: TRIREG = 1, DFM =1)
First transfer
Input pins
DB 2
DB 1
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
Second transfer DB DB DB 10 8 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
GRAM write data
WD [17]
WD [16]
WD [15]
WD [14]
WD [13]
WD [12]
WD [11]
WD [10]
WD [9]
WD [8]
WD [7]
WD [6]
WD [5]
WD [4]
WD [3]
WD [2]
WD [1]
WD [0]
RGB assignment
R5
R4
R3
R2
R1
B0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: Normal display in 262,144 colors
Figure 15 16-bit Interface Data Format (RAM data write)
RAM data read (one transfer: TRIREG = 0)
GRAM data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Read data
RD [17]
RD [16]
RD [15]
RD [14]
RD [13]
RD [12]
RD [11]
RD [10]
RD [9]
RD [8]
RD [7]
RD [6]
RD [5]
RD [4]
RD [3]
RD [2]
RD [1]
RD [0]
Output pins
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
Note: Data cannot be transferred in twice in read operation via 16-bit interface.
Figure 16 16-bit Interface Data Format (RAM data read)
Rev.1.21 April 9, 2007, page 103 of 205
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R61505U Data Transfer Synchronization in 16-bit Bus Interface operation The R61505U supports data transfer synchronization function to reset the counters for upper 16-/2-bit and lower 2-/16-bit transfers in 16-bit 2-transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 000H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 2/16 bits. The data transfer synchronization, when executed periodically, can help the display system recover from runaway. Make sure to execute data transfer synchronization after reset operation before transferring instruction.
RS
RD
WR
DB17 ~ DB10, DB8 ~ DB1
Upper Lower
"000"H
"000"H
"000"H
"000"H
Upper
Lower
Upper
(16-bit transfer synchronization)
Figure 17 16-bit Data Transfer Synchronization
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R61505U 80-system 9-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are transferred first (the LSB is not used). The RAM write data is also divided into upper and lower 9 bits, and the upper 9 bits are transferred first. The unused DB pins must be fixed at either IOVCC or IOGND level. When transferring the index register setting, make sure to write upper byte (8 bits).
IM[3:0] = 1011 CSn* A1 CS* RS WR* (RD*) DB17-9 DB8-0
H8/2245
HWR (RD*) D15-0
R61505U
9 9
Figure 18 9-bit interface
Instruction write
First transfer
Input
Second transfer
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
Device code read
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
First transfer
Output
Second transfer
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
instruction code
Figure 19 9-bit Interface Data Format (Instruction Write / Device Code Read)
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R61505U
RAM data write
1st transfer
Input
2nd transfer
DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
GRAM write data
R5
R4
R3
R2
R1
R0
G5
G4
G3
1 pixel
G2
G1
G0
B5
B4
B3
B2
B1
B0
Note:Normal display in 262,144 colors
RAM data read
GRAM data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Read data
RD RD [17] [16]
RD [15]
RD RD RD RD [14] [13] [12] [11]
RD [10]
RD [9]
RD [8]
RD [7]
RD [6]
RD [5]
RD [4]
RD [3]
RD [2]
RD [1]
RD [0]
Output pins
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
1st transfer
2nd transfer
Figure 20 9-bit Interface Data Format (RAM Data Write/ RAM Data Read)
Data Transfer Synchronization in 9-bit Bus Interface operation The R61505U supports data transfer synchronization function to reset the counters for upper and lower 9bit transfers in 9-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 9 bits. The data transfer synchronization, when executed periodically, can help the display system recover from runaway. Make sure to execute data transfer synchronization after reset operation before transferring instruction.
RS
RD
WR
Upper Lower
DB17 ~ DB9
"00"H
"00"H
"00"H
"00"H
Upper
Lower
Upper
(9-bit transfer synchronization)
Figure 21 9-bit Data Transfer Synchronization
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R61505U 80-system 8-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are transferred first. The RAM write data is also divided into upper and lower 8 bits, and the upper 8 bits are transferred first. The RAM write data is expanded into 18 bits internally as shown below. The unused DB pins must be fixed at either IOVCC or IOGND level. When transferring the index register setting, make sure to write upper byte (8 bits).
IM[3:0] = 0011 CSn* A1 CS* RS WR* (RD*) DB17-10 DB9-0
H8/2245
HWR (RD*) D15-0
R61505U
8
10
Figure 22 8-bit interface
Instruction write
First transfer
Input
Second transfer DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10
DB 17
DB 16
DB 15
DB 14
DB 13
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
Device code read
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
First transfer
Input
Second transfer DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10
DB 17
DB 16
DB 15
DB 14
DB 13
Figure 23 8-bit Interface Data Format (Instruction Write / Device Code Read)
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R61505U
RAM data write (2-transfer mode: TRIREG = 0)
First transfer
Input
Second transfer
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Note: 65,536-color display
RAM data write (3-transfer mode: TRIREG = 1, DFM =0)
First transfer
Input
DB 11
DB 10
DB 17
DB 16
Second transfer DB DB DB DB 15 14 13 12
DB 11
DB 10
DB 17
DB 16
DB 15
Third transfer DB DB DB 14 13 12
DB 11
DB 10
GRAM data write
R5
R4
R3
R2
R1
R0
G5
G4
G3
1 pixel
G2
G1
G0
B5
B4
B3
B2
B1
B0
Note: Normal display in 262,144 colors
RAM data write (3-transfer mode: TRIREG = 1, DFM = 1)
Input
DB 17
First transfer DB DB DB 16 15 14
DB 13
DB 12
DB 17
Second transfer DB DB DB DB 16 15 14 13
DB 12
DB 17
Third transfer DB DB DB 16 15 14
DB 13
DB 12
GRAM data write
R5
R4
R3
R2
R1
R0
G5
G4
G3
1 pixel
G2
G1
G0
B5
B4
B3
B2
B1
B0
Note: Normal display in 262,144 colors
Figure 24 8-bit Interface Data Format (RAM Data Write)
RAM data read
GRAM data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Read data
RD [17]
RD [16]
RD [15]
RD [14]
RD [13]
RD [12]
RD [11]
RD [10]
RD [9]
RD [8]
RD [7]
RD [6]
RD [5]
RD [4]
RD [3]
RD [2]
RD [1]
RD [0]
Output pins
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
1st transfer
2nd transfer Note: Data cannot be transferred in 3 times in read operation via 8-bit interface.
Figure 25 8-bit Interface Data Format (RAM Data Read)
Rev.1.21 April 9, 2007, page 108 of 205
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R61505U Data Transfer Synchronization in 8-bit Bus Interface operation The R61505U supports data transfer synchronization function to reset the counters for upper and lower 8bit transfers in 8-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 8 bits. The data transfer synchronization, when executed periodically, can help the display system recover from runaway. Make sure to execute data transfer synchronization after reset operation before transferring instruction.
RS
RD
WR DB17 ~ DB10
Upper Lower "00"H "00"H "00"H "00"H
Upper
Lower
Upper
(8-bit transfer synchronization)
Figure 26 8-bit Data Transfer Synchronization
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R61505U Serial Interface The serial interface is selected by setting the IM3/2/1 pins to the IOGND/IOVCC/IOGND levels, respectively. The data is transferred via chip select line (CS), serial transfer clock line (SCL), serial data input line (SDI), and serial data output line (SDO). In serial interface operation, the IM0/ID pin functions as the ID pin, and the DB17-0 pins, not used in this mode, must be fixed at either IOVCC or GND level. The R61505U recognizes the start of data transfer on the falling edge of CS input and starts transferring the start byte. It recognizes the end of data transfer on the rising edge of CS input. The R61505U is selected when the 6-bit chip address in the start byte transferred from the transmission unit and the 6-bit device identification code assigned to the R61505U are compared and both 6-bit data match. Then, the R61505U starts taking in subsequent data. The least significant bit of the device identification code is determined by setting the ID pin. Send "01110" to the five upper bits of the device identification code. Two different chip addresses must be assigned to the R61505U because the seventh bit of the start byte is register select bit (RS). When RS = 0, index register write operation is executed. When RS = 1, either instruction write operation or RAM read/write operation is executed. The eighth bit of the start byte is R/W bit, which selects either read or write operation. The R61505U receives data when the R/W = 0, and transfers data when the R/W = 1. When writing data to the GRAM via serial interface, the data is written to the GRAM after it is transferred in two bytes. The R61505U writes data to the GRAM in units of 18 bits by adding the same bits as the MSBs to the LSB of R and B dot data. After receiving the start byte, the R61505U starts transferring or receiving data in units of bytes. The R61505U transfers data from the MSB. The R61505U's instruction consists of 16 bits and it is executed inside the R61505U after it is transferred in two bytes (16 bits: DB15-0) from the MSB. The R61505U expands RAM write data into 18 bits when writing them to the internal GRAM. The first byte received by the R61505U following the start byte is recognized as the upper eight bits of instruction and the second byte is recognized as the lower 8 bits of instruction. When reading data from the GRAM, valid data is not transferred to the data bus until first five bytes of data are read from the GRAM following the start byte. The R61505U sends valid data to the data bus when it reads the sixth and subsequent byte data. Table 69 Start Byte Format
Transferred Bits Start byte format Note: S Transfer start 1 0 2 1 3 1 4 1 5 0 6 ID 7 RS 8 R/W Device ID code
The ID bit is determined by setting the IM0/ID pin.
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R61505U Table 70 Functions of RS, R/W bits
RS 0 0 1 1 R/W 0 1 0 1 Function Set index register Setting inhibited Write instruction or RAM data Read register settings or RAM data
Instruction
Input
D 15
D 14
D 13
First transfer (upper) D D D 12 11 10
Second transfer (Lower)
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
Input
D 15
D 14
D 13
First transfer (upper) D D D 12 11 10
Second transfer (Lower)
D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
GRAM write data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: 65,536-color display in SPI
Figure 27 Serial interface Data Format
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R61505U
(a) Clock synchronization serial data transfer (basic mode)
Transfer start End of transfer
CS input
1
SCL input
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MSB
LSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDI input
"0"
"1"
"1"
"1"
"0"
ID
RS
RW D15 D14 D13 D12 D11 D10
Device ID code Start byte
RS RW
Set IR (index register), instruction, write RAM data
SDO output
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read instruction, RAM data
(b) Clock synchronization serial consecutive data transfer
CS input SCL input
SDI input
Start byte
Instruction (1) Upper 8 bits
Instruction (1) Lower 8 bits
Instruction (2) Upper 8 bits
Instruction (2) Lower 8 bits End
Start Note: The eight bits read after start byte input is recognized as the upper byte of instruction. Instruction execution time (1)
(c) RAM read data transfer
CS input SCL input Start byte RS = 1 R/W = 1
SDI input
SDO output Start
Dummy read Dummy read Dummy read Dummy read Dummy read RAM read Upper 8 bits 5 1 2 3 4
RAM read Lower 8 bits End
Note: Valid data is not sent until the R61505U reads five bytes from the GRAM after start byte input . The R61505 sends valid data when it reads the sixth and subsequent bytes.
Figure 28 Data Transfer in Serial interface
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R61505U
VSYNC Interface
The R61505U supports VSYNC interface, which enables displaying a moving picture via system interface by synchronizing the display operation with the VSYNC signal. VSYNC interface can realize moving picture display with minimum modification to the conventional system operation.
VSYNC
LCDC/MPU
CS* RS WR* DB17-0, 8-1
R61505U
16
Figure 29 VSYNC Interface The VSYNC interface is selected by setting DM1-0 = 10 and RM = 0. In VSYNC interface operation, the internal display operation is synchronized with the VSYNC signal. By writing data to the internal RAM at faster than the calculated minimum speed (internal display operation speed + margin), it becomes possible to rewrite the moving picture data without flickering the display and display a moving picture via system interface. The display operation is performed in synchronization with the internal clock signal generated from the internal oscillator and the VSYNC signal. The display data is written in the internal RAM so that the R61505U rewrites the data only within the moving picture area and minimize the number of data transfer required for moving picture display. By writing data using high-speed write function (HWM =1), the R61505U can write data via VSYNC interface in high speed with low power consumption.
VSYNC
RAM data write via system interface Display operation synchronized with internal clock
Note: Use high-speed write function (HWM=1) when writing data via VSYNC interface.
Figure 30 Moving Picture Data Transfers via VSYNC Interface
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R61505U The VSYNC interface has the minimum for RAM data write speed and internal clock frequency, which must be more than the values calculated from the following formulas, respectively.
Internal clock frequency (fosc) [Hz] = FrameFrequency x ( DisplayLin es ( NL ) + FrontPorch ( FP ) + BackPorch( BP )) x 16(clocks ) x var iance
RAMWriteSpeed (min .)[ Hz ] >
240 x DisplayLines ( NL) ( BackPorch( BP) + DisplayLines( NL) - m arg ins ) x 16(clocks) x 1 fosc
Note: When RAM write operation is not started right after the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account. An example of calculating minimum RAM writing speed and internal clock frequency in VSYNC interface operation is as follows. [Example] Panel size Total number of lines (NL) Back/front porch Frame frequency 240 RGB x 320 lines (NL = 6'h27: 320 lines) 320 lines 14/2 lines (BP = 4h'E, FP = 4'h2) 65 Hz
Internal clock frequency (fosc) [Hz] = 65 Hz x (320 + 2 + 14) lines x 16 clocks x 1.07 / 0.93 = 402 kHz Notes: 1. When setting the internal clock frequency, possible causes of fluctuation must also be taken into consideration. In this example, the internal clock frequency allows for a margin of 10% for variances and guarantee that display operation is completed within one VSYNC cycle. 2. This example includes variances attributed to LSI fabrication process and room temperature. Other possible causes of variances, such as differences in external resistors and voltage change are not considered in this example. It is necessary to include a margin for these factors. Minimum speed for RAM writing [Hz] > 240 x 320 / {((14 + 320 - 2) lines x 16 clocks) x 1/402 kHz} = 5.81 MHz Notes: 1. 2. In this example, it is assumed that the R61505U starts writing data in the internal RAM on the falling edge of VSYNC. There must be at least a margin of 2 lines between the line to which the R61505U has just written data and the line where display operation on the LCD is performed.
In this example, the RAM write operation at a speed of 5.7MHz or more, which starts on the falling edge of VSYNC, guarantees the completion of data write operation in a certain line address before the R61505U starts the display operation of the data written in that line and can write moving picture data without causing flicker on the display.
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R61505U
VSYNC Back porch (14 lines) RAM write Display operation
[line] 320
RC oscillation 7%
FP = 2H
Main panel
Moving picture display (320 lines)
Line processing
RAM write 5.81 MHz
Display operation
Front porch (2 lines) Blank period BP = 14H VSYNC
0 13.22
15.38 [ms] (65 Hz)
Figure 31 Write/Display Operation Timing via VSYNC Interface Notes to VSYNC Interface operation 1. The above example of calculation gives a theoretical value. Possible causes of variances of internal oscillator should be taken into consideration. Make enough margin in setting RAM write speed for VSYNC interface operation. The above example shows the values when writing over the full screen. Extra margin will be created if the moving picture display area is smaller than that.
RAM write
2.
[line]
RC oscillation 7%
Back porch (14 lines)
(16 lines)
320
Display operation
FP = 2H
316
Moving picture display (320 lines)
Line processing
Base image
RAM write 5.81MHz
Display operation
(24 lines)
Front porch (2 lines)
VSYNC
16 0
BP = 14H
[ms] 15.38 (65 Hz)
Figure 32 RAM Write Speed Margins
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R61505U 3. 4. 5. 6. 7. The front porch period continues from the end of one frame period to the next VSYNC input. The instructions to switch from internal clock operation (DM1-0 = 00) to VSYNC interface operation modes and vice versa are enabled from the next frame period. The partial display and vertical scroll functions are not available in VSYNC interface operation. In VSYNC interface operation, set AM = 0 to transfer display data correctly. In VSYNC interface operation, use high-speed write function (HWM = 1) when writing display data to the internal RAM.
Internal Clock Operation to VSYNC Interface
VSYNC Interface to Internal Clock Operation
Internal clock operation
Operation via VSYNC interface
Display operation in synchronization with internal clocks Display operation in synchronizaion with VSYNC
HWM = 1 and AM = 0 RAM address set Set DM1-0 = 10 and RM = 0 for VSYNC interface Set index register R22h
Set DM1-0=00 and RM=0 for internal clock operation
*Instruction setting to VSYNC interface is enabled from the next frame period.
*Instruction setting to internal clock operation mode is enabled from the next frame.
Wait one frame period or more
Display operation in synchronization with internal clock
Internal clock operation Wait one frame period or more
Note: Continue VSYNC signal for at least one frame period after setting DM1-0 and RM bits to internal clock operation mode.
Write data to RAM via VSYNC interface
Display operation in synchronizaion with VSYNC
Operation via VSYNC interface
Internal Clock Operation Mode Setting (DM1-0=00, RM=0)
Note: Input the VSYNC signal before setting the DM1-0 and RM bits to VSYNC interface mode.
Wait one frame period or more Internal clock operation
Figure 33 Sequences to Switch between VSYNC and Internal Clock Operation Modes
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R61505U
FMARK Interface
In the FMARK interface operation, data is written to internal RAM via system interface synchronizing with the frame mark signal (FMARK), realizing tearing less video image while using conventional system interface. FMARK output position is set in units of line using FMP bit. Set the bit considering data transfer speed.
FMARK
LCDC /MPU
CS* RS WR* DB17-10,8-1
R61505U
16
Figure 34 Display synchronous data transfer interface In this operation, moving picture display is enabled via system interface by writing data at higher than the internal display operation frequency to a certain degree, which guarantees rewriting the moving picture RAM area without causing flicker on the display. The data is written in the internal RAM. Therefore, when moving picture is displayed, data is written only to the moving picture display area without using RGB or VSYNC interface, minimizing number of data transfer required for moving picture display. High-speed write function (HWM = 1) enables writing data in high speed with low power consumption.
FMARK
RAM data write via system interface Display operation synchronized with internal clock
Note: Use high-speed write function (HWM=1) when writing data via FMARK interface.
Figure 35 Moving Picture Data Transfers via FMARK function
When transferring data in synchronization with FMARK signal, minimum RAM data write speed and internal clock frequency must be taken into consideration. They must be more than the values calculated from the following equations.
Internal clock frequency (fosc) [Hz] = FrameFrequency x ( DisplayLin es( NL ) + FrontPorch( FP ) + BackPorch( BP )) x 16 ( clocks ) x var iance
RAMWriteSpeed (min .)[ Hz ] >
240 x DisplayLin es( NL ) ( FrontPorch( FP ) + BackPorch( BP ) + DisplayLin es( NL ) - m arg ins ) x 16 ( clocks ) x 1 fosc
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R61505U Note: When RAM write operation is not started immediately following the rising edge of FMARK, the time from the rising edge of FMARK until the start of RAM write operation must also be taken into account. Examples of calculating minimum RAM data write speed and internal clock frequency is as follows. [Example] Panel size Total number of lines (NL) Back/front porch Frame marker position (FMP) Frame frequency 240 RGB x 320 lines (NL = 6'h27) 320 lines 14/2 lines (BP = 4h'E, FP = 4'h2) Display end line: 320th (FMP = 9'h14E) 65 Hz
Internal clock frequency (fosc) [Hz] = 65 Hz x (320 + 2 + 14) lines x 16 clocks x 1.07 / 0.93 = 402 kHz Notes: 1.When setting the internal clock frequency, possible causes of fluctuation must also be taken into consideration. In this example, the internal clock frequency allows for a margin of 10% for variances and guarantee that display operation is completed within one FMARK cycle. 2.This example includes variances attributed to LSI fabrication process and room temperature. Other possible causes of variances, such as differences in external resistors and voltage change are not considered in this example. It is necessary to include a margin for these factors. Minimum speed for RAM writing [Hz] > 240 x 320 / {((2+14 + 320 - 2) lines x 16 clocks) x 1/402 kHz} = 5.81 MHz Notes: 1. In this example, it is assumed that the R61505U starts writing data in the internal RAM on the rising edge of FMARK. 2.There must be at least a margin of 2 lines between the line to which the R61505U has just written data and the line where display operation on the LCD is performed. 3.The FMARK signal output position is set to the line specified by FMP[8:0] bits.
In this example, RAM write operation at a speed of 5.81MHz or more, when starting on the rising edge of FMARK, guarantees the completion of data write operation in a certain line address before the R61505U starts the display operation of the data written in that line and can write moving picture data without causing flicker on the display.
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R61505U
FMARK
RAM write
Front porch (2 lines) Back porch (14 lines)
Display operation
[line] 320
RAM write (10MHz) 76,800 times
RC oscillation 7%
Line processing
RAM write 5.81MHz
Main panel
Moving picture display (320 lines)
Display operation
0
1+FP+BP=17H FMARK 7.68 13.22
[ms] 15.38 (65Hz)
Front porch (2 lines) Back porch (14 lines)
Figure 36
Notes to display operation synchronous data transfer using FMARK signal 1. The above example of calculation gives a theoretical value. Possible causes of variances of internal oscillator should be taken into consideration. Make enough margin in setting RAM write speed for this operation. 2. Use high-speed write function (HWM = 1).
FMP bit setting The microcomputer detects FMARK signal outputted at the position defined by FMP bit. The R61505U outputs an FMARK pulse when the R61505U is driving the line specified by FMP[8:0] bits. The FMARK signal can be used as a trigger signal to write display data in synchronization with display operation by detecting the address where data is read out for display operation. The FMARK output interval is set by FMI[2:0] bits. Set FMI[2:0] bits in accordance with display data rewrite cycle and data transfer rate. This setting is enabled when FMARKOE = 1.
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R61505U Table 71
FMP[8:0] 9'h000 9'h001 9'h002 : 9'h14D 9'h14E 9'h14F 9'h150 ~ 1FF FMARK output position 0 1 line 2nd line : 333 line 334 line 335th line Setting disabled
th rd st
Table 72
FMI[2] 0 0 0 1 FMI[1] 0 0 1 0 FMI[0] 0 1 1 1 FMARK Output interval One frame period 2 frame periods 4 frame periods 6 frame periods Setting disabled
Other setting
FMP setting example
FMARK output position FMP = 9'h008
Line address
0 (1st line) 1 (2nd line) 2 (3rd line) 3 (4th line) 4 (5th line) 5 (6th line) 6 (7th line) 7 (8th line) 8 (1st line) 9 (2nd line) 10 (3rd line)
FMP=9'h008 NL=6'h27 320th line FP=4'h8 BP=4'h8 VL=8'h00
Back porch RAM physical line address
AD[16:8] = 9'h000 AD[16:8] = 9'h001 AD[16:8] = 9'h002
Base image NL = 6'h27
Display area
327 (320th line) 328 (1st line) 329 (2nd line) 330 (3rd line) 331 (4th line) 332 (5th line) 333 (6th line) 334 (7th line) 335 (8th line)
AD[16:8] = 9'h13F
Front porch
Figure 37
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R61505U
External Display Interface
The R61505U supports the RGB interface. The interface format is set by RM[1:0] bits. The internal RAM is accessible via RGB interface. Table 73 RGB interface
RIM1 0 0 1 1 Note: RIM0 0 1 0 1 RGB Interface 18-bit RGB interface 16-bit RGB interface 6-bit RGB interface Setting inhibited DB Pin DB17-0 DB17-13, DB11-1 DB17-12 -
Using multiple interface at a time is prohibited.
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R61505U RGB Interface The display operation via RGB interface is synchronized with VSYNC, HSYNC, and DOTCLK. The data can be written only within the specified area with low power consumption by using window address function and high-speed write mode (HWM = 1). In RGB interface operation, front and back porch periods must be made before and after the display period.
VSYNC ENABLE (V)
Back porch period (BP)
Moving picture display area
Display period (NL)
Front porch period (FP)
HSYNC DOTCLK ENABLE (H) DB17-0
VSYNC: Frame synchronization signal HSYNC: Line synchronization signal DOTCLK: Dot clock ENABLE: Data enable signal DB 17-0: RGB (6:6:6) display data
Back porch period (BPP): Front porch period (FPP): Display period: The number of lines for one frame:
14H BP 2H 14H FP 2H FPP + BPP 16H NL 320H FPP + NL + BPP
Notes: 1. The front porch period continues until next VSYNC input is detected. 2. Make sure to match the VSYNC, HSYNC, and DOTCLK frequencies to the resolution of liquid crystal panel.
Figure 38 Display Operation via RGB Interface
Polarities of VSYNC, HSYNC, ENABLE, and DOTCLK Signals The polarities of VSYNC, HSYNC, ENABLE, and DOTCLK signals can be changed by setting the DPL, EPL, HSPL, and VSPL bits, respectively for convenience of system configuration.
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R61505U RGB Interface Timing The timing relationship of signals in RGB interface operation is as follows. 16-/18-bit RGB Interface Timing
One frame Back porch period Front porch period
VSYNC
HSYNC
DOTCLK
ENABLE
DB17-0
VLW = 1H or more
VSYNC
1H HLW 1CLK
HSYNC
1 clock
DOTCLK
DTST
ENABLE
1CLK
DB17-0
Valid data
Figure 39
Notes: 1. VLW: VSYNC Low period HLW: HSYNC Low period DTST: data transfer setup time 2. Use high-speed write function (HWM = 1) when writing data via RGB interface.
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R61505U 6-bit RGB Interface Timing
One frame Back porch period Front porch period
VSYNC HSYNC DOTCLK ENABLE DB17-12
VLW = 1H or more
VSYNC
1H
HLW 3CLK
HSYNC
1CLK
DOTCLK
DTST 3CLK
ENABLE
RGBRGBRGBRGBRGBRGBRGB
DB17-12
Valid data
Figure 40 Notes: 1. VLW: VSYNC Low period HLW: HSYNC Low period DTST: Data transfer setup time 2. Use high-speed write function (HWM = 1) when writing data via RGB interface. 3. In 6-bit RGB interface operation, set the VSYNC, HSYNC, ENABLE, DOTCLK cycles so that one pixel is transferred in units of three DOTCLKs via DB17-12.
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R61505U Moving Picture Display via RGB Interface The R61505U supports RGB interface for moving picture display and incorporates RAM for storing display data, which provides the following advantages in displaying a moving picture. 1. The window address function enables transferring data only within the moving picture area 2. The high-speed write function enables RAM access in high speed with low power consumption 3. It becomes possible to transfer only the data written over the moving picture area 4. By reducing data transfer, it can contribute to lowering the power consumption of the whole system 5. The data in still picture area (icons etc.) can be written over via system interface while displaying a moving picture via RGB interface RAM access via system interface in RGB interface operation The R61505U allows RAM access via system interface in RGB interface operation. In RGB interface operation, data is written to the internal RAM in synchronization with DOTCLK while ENABLE is "Low". When writing data to the RAM via system interface, set ENABLE "High" to stop writing data via RGB interface. Then set RM = "0" to enable RAM access via system interface. When reverting to the RGB interface operation, wait for the read/write bus cycle time. Then, set RM = "1" and the index register to R22h to start accessing RAM via RGB interface. If there is a conflict between RAM accesses via two interfaces, there is no guarantee that the data is written in the RAM. The following is an example of rewriting still picture data via system interface while displaying a moving picture via RGB interface.
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R61505U
updating frame data VSYNC updating frame data
ENABLE
DOTCLK
DB17-0
Note 4) System interface
RAM address set Update data in the area other than moving picture area RAM address set
Note 4)
Index R22
RM = 0
writing moving picture area
Index R22
RM = 1
Index R22
writing moving picture area
writing still picture area
Notes:
1. In RGB interface operation, RAM address AD16-0 is set in the address counter on the falling edge of VSYNC. 2. Set AD16-0 bits and the index R22h before starting RAM access via RGB interface. 3. Use high-speed write function when writing via RGB interface. 4. When switching to the system interface operation after writing data via RGB interface, wait at least one write cycle (tcycw).
6/25 00:00 6/2 00:00 6/25 00:00 6/2 00:00
Moving picture area
Moving picture area
Figure 41 Updating the Still Picture Area while Displaying Moving Picture
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R61505U 6-bit RGB interface The 6-bit RGB interface is selected by setting RIM1-0 = 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 6-bit port while data enable signal (ENABLE) allows RAM access via RGB interface. Unused pins DB11-0 must be fixed at either IOVCC or IOGND level. Instruction bits can be transferred only via system interface.
RIM = 10 VSYNC
LCDC /MPU
HSYNC DOTCLK
R61505U
ENABLE DB17-12 DB11-0
6
12
Data format for the 6-bit RGB interface (RIM = 10) Input
RIM = 10
DB 17
DB 16
First transfer DB DB DB 15 14 13
Second transfer DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16
Third transfer DB DB DB 15 14 13
DB 12
GRAM write data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: 262,144 colors
Figure 42 Example of 6-bit RGB Interface and Data Format
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R61505U Data Transfer Synchronization in 6-bit Bus Interface operation The R61505U has the counters, which count the first, second, third 6 bit transfers via 6-bit RBG interface. The counters are reset on the falling edge of VSYNC so that the data transfer will start from the first 6 bits of 18-bit RGB data from the next frame period. Accordingly, the data transfer via 6-bit interface can restart in correct order from the next frame period even if a mismatch occurs in transferring 6-bit data. This function can minimizes the effect from data transfer mismatch and help the display system return to normal display operation when data is transferred consecutively in moving picture operation.
VSYNC
ENABLE
DOTCLK
DB17-12
Second transfer Second Third First First Second Third transfer transfer transfer transfer transfer transfer
Transfer synchronization
Figure 43 6-bit Transfer Synchronization
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R61505U 16-bit RGB interface The 16-bit RGB interface is selected by setting RIM1-0 = 01. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 16-bit ports while data enable signal (ENABLE) allows RAM access via RGB interface. Instruction bits can be transferred only via system interface.
RIM = 001 VSYNC HSYNC
LCDC/MPU
DOTCLK
R61505U
ENABLE DB17-13, 11-1
16
2
DB12,0
Data format for the16-bit interface (RIM = 01)
Input
DB 17
DB 16
DB 15
DB 14
DB 13
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
GRAM data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: 65,536-color display
Figure 44 Example of 16-Bit RGB Interface and Data Format
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R61505U 18-bit RGB interface The 18-bit RGB interface is selected by setting RIM1-0 = 00. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 18-bit ports (DB17-0) while data enable signal (ENABLE) allows RAM access via RGB interface. Instruction bits can be transferred only via system interface.
RIM = 00 VSYNC HSYNC
LCDC/MPU
DOTCLK
R61505U
ENABLE DB17-0
18
Data format for the 18-bit interface (RIM = 00)
Input
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
GRAM write data
R5
R4
R3
R2
R1
R0
G5
G4
G3
1 pixel
G2
G1
G0
B5
B4
B3
B2
B1
B0
Note: Normal display in 262,144 colors
Figure 45 Example of 18-bit RGB Interface and Data Format
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R61505U Notes to external display interface operation a. The following functions are not available in external display interface operation. Table 74 Functions Not Available in External Display Interface operation
Function Partial display Scroll function External Display Interface Not available Not available Internal Display Operation Available Available
b. The VSYNC, HSYNC, and DOTCLK signals must be supplied during display period. c. The reference clock to generate liquid crystal panel controlling signals in RGB interface operation is DOTCLK, not the internal clock generated from the internal oscillator. d. In 6-bit RGB interface operation, 6-bit dot data (R, G, and B) is transferred in synchronization with DOTCLK. In other words, it takes three DOTCLKs to transfer one pixel data. e. In 6-bit RGB interface operation, make sure to set the cycles of VSYNC, HSYNC, DOTCLK, ENABLE signals so that the data transfer is completed in units of pixels. f. When switching between the internal operation mode and the external display interface operation mode, follow the sequences below in setting instruction. g. In RGB interface operation, front porch period continues after the end of frame period until next VSYNC input is detected. h. In RGB interface operation, use high-speed write function (HWM = 1) when writing data to the internal RAM. i. In RGB interface operation, RAM address AD16-0 is set in the address counter every frame on the falling edge of VSYNC.
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R61505U
Internal Clock Operation to RGB Interface (1) RGB Interface (1) to Internal Clock Operation
Internal clock operation
HWM = 1 and AM = 0 RAM address set Set DM1-0 = 01 and RM = 1 for RGB interface Set index register to R22h Wait one frame period or more Write data to RAM via RGB interface Display operation in synchronization with internal clocks
*Instruction setting for the RGB interface operation is enebled from the next frame period.
RGB interface operation Set internal clock operation mode* (DM1-0 = 00 and RM = 0) Wait one frame period or more
Display operation in synchronization with VSYNC, HSYNC, and DOTCLK
*Instruction setting to the internal clock operation is enebled from the next frame period.
Internal clock operation
Display operation in synchronization with internal clocks
Note: Continue RGB interface signals at least for one frame period after setting DM1-0, RM bits to internal clock operation.
Display operation in synchronization with VSYNC, HSYNC, and DOTCLK
Operation via RGB interface
Note: Input the RGB interface signals before setting the DM1-0 and RM bits to the RGB interface operation.
Figure 46 RGB and Internal Clock Operation Mode switching sequences
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R61505U
RAM Address and Display Position on the Panel
The R61505U has memory to store display data of 240RGB x 320 lines. The R61505U incorporates a circuit to control partial display, which allows switching driving method between full-screen display mode and partial display mode. The R61505U makes display arrangement setting and panel driving position control setting separately and specifies RAM area for each image displayed on the panel. For this reason, there is no need to take the mounting position of the panel into consideration when designing a display on the panel. The following is the sequence of setting full-screen and partial display. 1. 2. 3. 4. Set (PTSAx, PTEAx) to specify the RAM area for each partial image Set the display position of each partial image on the base image by setting PTDPx. Set NL to specify the number of lines to drive the liquid crystal panel to display the base image After display ON, set display enable bits (BASEE, PTDE0/1) to display respective images Normal display Partial display 1/2 5. BASEE = 1 BASEE = 0, PTDE0/1 = 1
Changes BASEE, PTDE0/1 settings when turning on and off the full and partial displays 1/2.
In driving the liquid crystal panel, the clock signal for gate line scan is supplied consecutively via interface in accordance with the number of lines to drive the liquid crystal panel (NL setting). When switching the display position in horizontal direction, set SS bit when writing RAM data. Table 75
Display ENABLE Base image BASEE Numbers of lines NL RAM area (BSA, BEA) = (9'h000, 9'h13F)
Notes 1: The base image is displayed from the first line of the screen. 2: Make sure NL 320 (lines) = BEA - BSA when setting a base image RAM area. BSA and BEA are fixed to 9'h000, 9'h13F, respectively. Table 76
Display ENABLE Partial image 1 Partial image 2 PTDE0 PTDE1 Display position PTDP0 PTDP1 RAM area (PTSA0, PTEA0) (PTSA1, PTEA1)
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R61505U
Panel display position Display data output position 1 BSA = 9'h000
LCD
Base image RAM Address
Partial image RAM Address
RAM Write Address
(HSA,HEA)
PTDP0
Scan direction Base image
PTSA0
Partial image 1 Window Address (VSA,VEA)
PTEA0 PTSA1
Partial image 2
PTDP1
NL
PTEA1
BEA = 9'h13F
Figure 47 RAM Address, display position and drive position Restrictions in setting display control instruction There are restrictions in coordinates setting for display data, display position and partial display. Screen setting In setting the number of lines to drive the liquid crystal panel, make sure that the total number of lines is 320 lines or less (NL 320 lines). Base image display 1. 2. The base image is displayed from the first line of the screen: BSA = 1st line (of the display panel) The base image RAM area (specified by BSA = 000, BEA = 13F) must include the same or more number of lines set by NL bits (liquid crystal panel drive lines): BEA - BSA = 320 lines NL
Partial image display Set the partial image RAM area setting registers (PTSAx, PTEAx bits) and the partial position setting registers (PTDPx bits) so that the RAM areas and the display positions of partial images do not overlap one another. 0 PTDP0 PTDP0+ (PTEA0 - PTSA0) < PTDP1 PTDP1+ (PTEA1 - PTSA1) NL
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R61505U The following figure shows the relationship among the RAM address, display position, and the lines driven for the display.
Display data output order
LCD panel physical line address
RAM line address
0 1 2 3 4 5
Display screen
0 (1st line) 1 (2nd line) 2 (3rd line)
Partial display
BSA0 = 9'h000
PTDP0 PTSD image 1 Display area PTDP1 NL (n lines) PTSD image 2 Display area BASE image RAM area
NL
n-1
NL PTSA0 Partial image 1 RAM area PTEA0 PTSA1 Partial image 2 RAM area PTEA1
BEA = 9'h13F
Figure 48 Display RAM address and panel display position Note: This figure shows the relationship between RAM line address and the display position on the panel. In the R61505U's internal operation, the data is written in the RAM area specified by the window address setting (R50h~R53h).
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R61505U Instruction setting example The followings are examples of settings for 240(RGB) x 320(lines) panel. 1. Full screen display (no partial display)
The following is an example of settings for full screen display. Table 77
Base image display instruction BASEE 1 NL[5:0] 6'h27 PTDE0 PTDE1 0 0
Display data output order
1 2 3 4 5
LCD panel physical line address
0 (1st line) 1 (2nd line) 2 (3rd line)
RAM line address
BSA=9'h000 9'h000
NL (320 lines)
Base image
BASE image RAM area
320
319 (320th line)
BEA = 9'h13F
Figure 49 Full screen display (no partial)
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R61505U 2. Partial Display
The following is an example of settings for displaying partial image 1 only and turning off the base image. The partial image 1 is displayed at the position specified by PTDP0 bit. Table 78
Base image display instruction BASEE 0 NL[5:0] 6'h27 partial image 1 display instruction PTDE0 1 PTSA0[8:0] 9'h000 PTEA0[8:0] 9'h00F PTDP0[8:0] 9'h080 partial image 2 display instruction PTDE1 0 PTSA1[8:0] 9'h000 PTEA1[8:0] 9'h000 PTDP1[8:0] 9'h000
Display data output order
1 2 3 4 5
LCD panel physical line address
0 (1st line) 1 (2nd line) 2 (3rd line)
RAM line address
PTSA0 = 9'000 Partial image 1 RAM area PTEA0 = 9'h00F PTDP0
Partial image display area
BASE image RAM area
NL (320 lines)
Base image (non-lit display)
320
319 (320th line)
BEA = 9'h13F
Figure 50 Partial Display
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R61505U
Resizing function
The R61505U supports resizing function (x 1/2, x 1/4), which is performed when writing image data. The resizing function is enabled by setting a window address area and the RSZ bit representing the contraction factor (x1/2 or x1/4) of the image. This function enables the R61505U to write the resized image data directly to the internal RAM, while allowing the system to transfer the original-sized image data. The resizing function allows the system to transfer data as usual even when resizing of the image is required. This feature makes image resizing easily available with various applications such as camera display, sub panel display, thumbnail display and so on. The R61505U processes the contraction of an image simply by selecting pixels. For this reason, the resized image may appear distorted when compared with the original image. Check the resized image before use.
Original image data
0 0 1 2 3 4 5 6 (0,0) (1,0) (2,0) (3,0) (4,0) (5,0) (6,0) 1 (0,1) (1,1) (2,1) (3,1) (4,1) (5,1) (6,1) 2 (0,2) (1,2) (2,2) (3,2) (4,2) (5,2) (6,2) 3 (0,3) (1,3) (2,3) (3,3) (4,3) (5,3) (6,3) 4 (0,4) (1,4) (2,4) (3,4) (4,4) (5,4) (6,4) 5 (0,5) (1,5) (2,5) (3,5) (4,5) (5,5) (6,5) 6 (0,6) (1,6) (2,6) (3,6) (4,6) (5,6) (6,6)
RAM data 1/2 resizing
0 0 1 2 3 (0,0) (2,0) (4,0) (6,0) 1 (0,2) (2,2) (4,2) (6,2) 2 (0,4) (2,4) (4,4) (6,4) 3 (0,6) (2,6) (4,6) (6,6)
Figure 51 Data transfer in resizing
Original data
240
Panel Display R61505U RAM data
RSZ=2'h1
120 160
320
RAM Write
Figure 52 Data transfer, display example in resizing Table 79
Original image size (X x Y) 640x480(VGA) 352x288 (CIF) 320x240 (QVGA) 176x144 (QCIF) 120x160 132x176 1/2 (RSZ = 2'h1) 320x240 176x144 160x120 88x72 60x80 66x88 Resized image size 1/4 (RSZ = 2'h3) 160x120 88x72 80x60 44x36 30x40 33x44
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R61505U Resizing setting The RSZ bit sets the resizing (contraction) factor of an image. When setting a window address area in the internal RAM, the window address area must fit the size of the resized picture. If there are surplus pixels as a result of resizing, which are calculated from the following equations, set RCV, RCH bits to the number of surplus pixels before writing data to the internal RAM.
R61505U GRAM Address
X (X0,Y0)
Formulas for calculating the number of surplus pixels
Rx
The number of surplus pixels in horizontal direction
L = X mod N
Orizinal image data
Y Ry RAM write data (1/N resizing)
The number of surplus pixels in vertical direction
M = Y mod N
Resized picture size in horizontal direction
(X0+Rx-1,Y0+Ry-1)
Rx = (X-L)/N
Resized picture size in vertical direction
Ry = (Y-M)/N
Figure 53 Resizing Setting, surplus pixel calculation
Table 80 Image (before resizing)
Number of data in horizontal direction Number of data in vertical direction Resizing ratio X Y 1/N
Register setting in the R61505U
Resizing setting Number of data in horizontal direction Number of data in vertical direction RAM writing start address RAM window address RSZ RCV RCH AD HSA HEA VSA VEA N-1 L M (X0, Y0) X0 X0+Rx - 1 Y0 Y0+Ry - 1
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R61505U Example of 1/2 resizing
Rx=120 RAM write data (1/2 resizing) 120 x 160 R61505U GRAM address
X=240
(0,0)
Ry=160
Y=320
Original Image 240 x 320
(119, 159)
Figure 54
Resizing setting example (x 1/2)
Table 81 Original image (before resizing)
Number of data in horizontal direction Number of data in vertical direction Resizing ratio X Y 1/N 240 320 1/2
Register setting in the R61505U
Resizing setting Number of data in horizontal direction Number of data in vertical direction RAM writing start address RAM window address RSZ RCV RCH AD HSA HEA VSA VEA 2'h1 2'h0 2'h0 17'h00000 8'h00 8'h77 8'h00 8'h9F
Resizing instruction Table 82
RSZ[1:0] 2h'0 2h'1 2h'2 2h'3 2h'4
Resizing factor Contraction factor
No resizing (x 1) 1/2 resizing (x 1/2) Setting disabled 1/4 resizing (x 1/4) Setting disabled
Table 83
RCV[1:0] 2h'0 2h'1 2h'2 2h'3
Surplus pixels horizontal direction
RCH[1:0] 2h'0 2h'1 2h'2 2h'3 Surplus pixels 0 1 pixel 2 pixels 3 pixels
1 pixel = 1 RGB
Vertical direction
Surplus pixels 0 1 pixel 2 pixels 3 pixels
1 pixel = 1 RGB
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R61505U Notes to Resizing function 1. 2. 3. 4. 5. Set the resizing instruction bits (RSZ, RCV, and RCH) before writing data to the internal RAM. When writing data to the internal RAM using resizing function, make sure to start writing data from the first address of the window address area in units of lines. Set the window address area in the internal RAM to fit the size of the resized image. Set AD16-0 (R20h, R21h) before start transferring and writing data to the internal RAM. Set the RCH, RCV bits only when using resizing function and there are surplus pixels. Otherwise (if RSZ = 2'h0), set RCH = RCV = 2'h0.
Resizing instruction (RSZ, RCH, RCV)
Set a window address area (HSA, HEA, VSA, VEA)
Set the size of the window address area to fit the size of the resized image
RAM address set (AD16-0)
Write data to RAM
Figure 55 RAM write operation sequence in resizing
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R61505U
High-speed RAM Write Function
The R61505U supports high-speed RAM write function to write data to each line of window address area at a time. This function makes the R61505U available with the applications, which require high-speed, low-power-consumption data write operation such as color moving picture display. When enabling high-speed RAM write function (HWM = "1"), the data is first stored in the internal register of the R61505U in order to rewrite the RAM data in each horizontal line of the window address area at a time. Also, when transferring the data from the internal register to the internal RAM, the data written in the next line of the window address area can be transferred to the internal register of the R61505U. The high-speed write function minimizes the number of RAM access in write operation and enables high-speed consecutive RAM write operation required for moving picture display with low power consumption.
Microcomputer
Latch circuit
18
Address counter (AC) 17
Register 1
Register 2
............... 18 x n
Register n
17'h0-0000 17'h0-0001
...........
17'h0-0003
GRAM
Figure 56 High-speed Consecutive RAM Write Operation
CS input
1
WR input
2
...
n
1
2
...
n
1
2
...
n
RAM data DB17-0 input Index (R22) (1) (2) ... (n) (1) (2) ... (n) (1) (2) ... (n) Index (R22)
RAM write execution time
RAM write execution time
RAM write execution time x 2*
RAM write data (18 x n bits)
RAM data (1) - (n)
RAM data (n + 1) - (2n)
RAM data (2n + 1) - (3n)
RAM address (AD16-0)
17'h00000 - 17'h0000n
17'h00100 - 17'h0010n
17'h00200 - 17'h0020n
Figure 57 Example of High-speed RAM Write Operation (HWM = 1) Note: When switching from high-speed RAM write operation to index write operation, wait at least for two normal RAM write bus cycle periods (2 x tcycw) before executing a next instruction.
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R61505U
CS
input
1 WR 2 .......... 3 4 5 6 .......... 7 8
input
DB17-0 input
Index (R202)
RAM data upper (1)
RAM data lower (1)
....
RAM data upper (n)
RAM data lower (n)
RAM data upper (1)
RAM data lower (1)
....
RAM data upper (n)
RAM data lower (n)
RAM write execution time
RAM write execution time
RAM write dat a (18 x n bits)
RAM data (1) - (n)
RAM data (n + 1) - (2n)
RAM address (AD16-0)
17'h00000 - 17'h0000n
17'h00100 - 17'h0010n
Figure 58 Example of High-speed RAM Write Operation via 9-bit Interface Note: In high-speed RAM write operation, the R61505U writes data in units of n words. When using 9bit interface, the R61505U performs write operation 2 x n times in the internal register before writing the data in each line of the window address area.
Notes to high-speed RAM write function 1. In high-speed RAM write mode, the R61505U performs write operation to the internal RAM in units of lines. If the data inputted to the internal write register is not enough to rewrite the data in the horizontal line of the window address area, the data is not written correctly in that line address. If the IR is set to 22h when HWM = "1", the R61505U always performs RAM write operation. With this setting, the R61505U does not perform RAM read operation. Make sure to set HWM = 0, when performing RAM read operation. The high-speed RAM write function cannot be used when writing data in normal RAM write function mode. When switching form one write mode to the other, change modes first and set AD16-0 (RAM address set) before starting write operation.
2.
3.
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R61505U Table 84 RAM Write Operation
Normal RAM Write (HWM = 0) BGR function RAM address set RAM read RAM write Window address Available In units of words In units of words In units of words In units of words (minimum window address area: 1 word x 1 line) Available AM = 1/0 High-speed RAM Write (HWM = 1) Available In units of words Not available In units of words In units of words (minimum window address area: 8 words x 1 line) Available AM = 0
External display interface AM
High-speed RAM data write in a window address area The R61505U can perform consecutive high-speed data rewrite operation within a rectangular area (minimum: 8 words x 1 line) made in the internal RAM with the following settings. When writing data to the internal RAM using high-speed RAM write function, make sure each line of the window address area is overwritten at a time. If the data buffered in the internal register of the R61505U is not enough to overwrite the horizontal line in the window address area, the data is not written correctly in that line. The following is an example of writing data in the window address area using high-speed write function when a window address area is made by setting HSA = 8'h12, HEA = 8'hA7, VSA = 9'h020, and VEA = 9'h05B.
Write in horizontal direction AM = 0, I/D0 = 1 Window address setting area HSA = 8'h12, HEA = 8'hA7 VSA = 9'h020, VEA = 9'h05B
17'h00000
GRAM addr ess map
17h'02012
Enable High speed RAM write HW M = 1
Window address area (data rewrite area)
RAM address set AD = 17'h02012* see Note
17'h05BA7
17'h13FEF
RAM write x 150 times x 60 times Note: Set a RAM address within the window address area.
Window address area HSA = 8'h12, HEA = 8'hA7 VSA = 9'h020,VEA = 9'h05B
Figure 59 High-speed RAM Write Operation in the Window Address Area
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R61505U
Window Address Function
The window address function enables writing display data consecutively in a rectangular area (a window address area) made in the internal RAM. The window address area is made by setting the horizontal address register (start: HSA7-0, end: HEA 7-0 bits) and the vertical address register (start: VSA8-0, end: VEA8-0 bits). The AM and I/D bits set the transition direction of RAM address (either increment or decrement, horizontal or vertical, respectively). Setting these bits enables the R61505U to write data including image data consecutively without taking the data wrap position into account. The window address area must be made within the GRAM address map area. Also, the AD16-0 bits (RAM address set register) must be set to an address within the window address area. [Window address area setting range] (Horizontal direction) (Vertical direction) [RAM Address setting range] (RAM address)
8'h00 HSA < HEA 8'hEF 9'h000 VSA < VEA 9'h13F HSA AD7-0 HEA VSA AD16-8 VEA
GRAM address map
17'h00000 17'h000EF
Window address area
17'h02010 17'h02110 17'h0202F 17'h0212F
17'h05F10
17'h05F2F
17'h13F00
17'h13FEF
Window address area
HSA = 8'h10, HEA = 8'h2F VSA = 9'h020, VEA = 9'h05F I/D = 2'h3 (increment) AM = 1'h0 (horizontal writing)
Both are set to the same RAM address.
ORG = 0 RAM address set = 17'02010 (arbitrary) ORG = 1 RAM address set = 17'00000
Figure 60 Automatic address update within a Window Address Area
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R61505U
Scan Mode Setting
The R61505U can set the gate pin assignment and the scan direction in the following 4 different ways by setting SM and GS bits to realize various connections between the R61505U and the LCD panel.
SM
Scan direction
Interchanging forward direction (GS=0) Interchanging backward direction (GS=1)
1 3
2 4
320 318
319 317
320
main Panel (GS0)
320
main Panel (GS1)
0
317 176 319 318 320
R61505U
(Non-bump view)
240
4 2 176
240
3 1
R61505U
(Non-bump view)
Scan order (Gate line No.) G1 G2 G3 G4.... G317 G318 G319 G320
Scan order (Gate line No.) G320 G319 G318 G317 .... G4 G3 G2 G1
Left/right forward direction (GS=0)
Left/right backward direction (GS=1)
1 2
main Panel (GS0)
320 318
main Panel (GS1)
159 160
320
161 162
162 161
320
160 159
1
240
319 320
240
2 1
R61505U
(Non-bump view)
R61505U
(Non-bump view)
Scan order (Gate line No.) G1 G3.... G317 G318 G320 G319 G2 G4....
Scan order (Gate line No.) G320 G318 .... G4 G3 G1 G2 G319 G317 ....
Note: the numbers in the circles in the figure shows the order of scan.
Figure 61
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R61505U
8-color Display Mode
The R61505U has a function to display in eight colors. In this display mode, only V0 and V31 are used and power supplies to other grayscales (V1 to V30) are turned off to reduce power consumption. In 8-color display mode, the -adjustment registers P0KP0-P0KP5, P0KN0-P0KN5, P0RP0, P0RP1, P0RN0, P0RN1, P0FP0-P0FP3, and P0FN0-P0FN3, are disabled and the power supplies to V1 to V30 are halted. The R61505U does not require GRAM data rewrite for 8-color display by writing the MSB to the rest in each dot data to display in 8 colors.
MSB Display data R5 R4 R3 R2 R1 R0
GRAM
LSB B5 B4 B3 B2 B1 B0
G5 G4 G3 G2 G1 G0
Grayscale amplifier
V0 R5 2
Two-level grayscale control
G5
Two-level grayscale control
B5
Two-level grayscale control

V31
LCD driver
LCD driver
LCD driver
RGB
LCD
Figure 62 8-color Display Mode
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R61505U
Line Inversion AC Drive
The R61505U supports n-line inversion alternating current drive in addition to frame-inversion liquid crystal alternating current drive. The timing to invert the electric current can be set to either every line or every two lines. Set line number of inversion timing checking display quality on liquid crystal display. Note that less number of line leads to higher inversion frequency of liquid crystal and more charge/discharge battery in liquid crystal display.
One frame Back porch 1 Frame-inversion AC drive * 320 line drive 2 3 4 Front porch Back porch 2 3 4 One frame Front porch 321 322 336
321322
336 1
Line inversion AC drive * 320 line drive
Figure 63 Example of Alternating Signals for n-line Inversion
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R61505U Alternating Timing The following figure illustrates the liquid crystal polarity inversion timing in different LCD driving methods. In case of frame-inversion AC drive, the polarity is inverted as the R61505U draws one frame, which is followed by a blank period lasting for (BP+FP) periods. In case of line inversion AC drive, polarity is inverted as the R61505U draws one line, and a blank period lasting for (BP+FP) periods is inserted when the R61505U draws one frame.
Flame-inversion AC drive
Alternating timing
Line-inversion AC drive
Back porch
Alternating timing Alternating timing Alternating timing
Back porch 1 line 1 line 1 line 1 line 1 line 1 line 1 line 1 line 1 line 1 line Front porch
One-frame period
One-frame period
Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing
Frame 1
Alternating timing
Alternating timing Alternating timing
Front porch
Figure 64 Alternating Timing Note: Frame inversion AC drive is available only in 8-color display mode. Check the quality of display on the panel.
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R61505U
Frame-Frequency Adjustment Function
The R61505U supports a function to adjust frame frequency. The frame frequency for driving liquid crystal can be adjusted by setting the DIV, RTN bits without changing the oscillation frequency. The R61505U allows changing the frame frequency depending on whether moving picture or still picture is displayed on the screen. In this case, set a high oscillation frequency. By changing the DIV and RTN settings, the R61505U can operate at high frame frequency when displaying a moving picture, which requires the R61505U to rewrite data in high speed, and it can operate at low frame frequency when displaying a still picture. Relationship between liquid crystal drive duty and frame frequency The following equation represent the relationship between liquid crystal drive duty and frame frequency. The frame frequency can be changed by setting the 1H period adjustment bit (RTN) and the operation clock frequency division ratio setting bit (DIV). Equation for calculating frame frequency
FrameFrequency =
fosc [ Hz ] NumberofClocks / line x DivisionRatio x ( Line + FP + BP)
fosc: RC oscillation frequency Number of clocks per line: RTN bit Division ratio: DIV bit Line: number of lines to drive the LCD panel (NL bit) Number of lines for front porch: FP Number of lines for back porch: BP Example of Calculation: when maximum frame frequency = 70 Hz Fosc: 376KHz Number of lines: 320 lines 1H period: 16 clock cycles (RTNI/E[4:0] = "10000") Division ratio of operating clock: 1/1 Front porch: 2 lines Back porch: 14 lines FFLM=376KHz/(16 clocks x 1/1 x (320 + 2 + 14) (lines) = 70Hz
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R61505U
Partial Display Function
The partial display function allows the R61505U to drive lines selectively to display partial images by setting partial display control registers. The lines not used for displaying partial images are driven at nonlit display level to reduce power consumption. The power efficiency can be enhanced in combination with 8-color display mode. Check the display quality when using low power consumption functions.
Non-display area
G41
Partial image 1 19 lines
G59
Non-display area
Number of lines to drive LCD Base picture display ENABLE Partial image 1 display RAM area Partial image 1 display position Parital image 1 display ENABLE
: NL = 6'h1D (320 lines) : BASEE = 0 : (PTSA0, PTEA0) = (9'h000, 9'h013) : PTDP0 = 9'h028 : PTDE0 = 1
Figure 65 Partial display Note: See the "RAM Address and Display Position on the Panel" (p.133) for details on the relationship between the display positions of partial images and respective RAM area setting.
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R61505U
Liquid crystal panel interface timing
The relationships between RGB interface signals and liquid crystal panel control signals in internal operation and RGB interface operations are as follows Internal clock operation
1 Frame
reference point reference point reference point reference point reference point reference point reference point reference point
1H
FMARK
(FMP = BP - 1) NOWI
G1 G2 G320
MCPI
S(3n+1) S(3n+2) S(3n+3)
R, G, B
R, G, B
R, G, B
n=0 ~ 239
1st line
2nd line
320th line
VCOM
Figure 66
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R61505U RGB interface operation
1 Frame
BP FP
VSYNC
1H
HSYNC
DOTCLK
ENABLE
DB
1
2
3
4
5
6
318
319
320
1
2
3
5DOTCLK see Note
reference point
reference point
1H
FMARK
(FMP = BP = 1) NOWE
G1 G2 G3 G320
MCPE
S(3n+1) S(3n+2) S(3n+3)
n= 0 ~ 239
RGB
RGB
RGB
320
1
1st line 2nd line
3rd line
320th line
VCOM
Note: Transfer RGB data in one transfer via 16-bit port
Figure 67
Rev.1.21 April 9, 2007, page 153 of 205
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R61505U
Oscillator
The R61505U incorporates necessary RC elements for oscillator, eliminating the need to connect external elements for RC oscillation. The R61505U has two versions, each with different oscillation frequency: Typ. 376kHz (R61505U0) and Typ. 600kHz (R61505U). See "Electrical Characteristics" for details. Select either suitable for display system. Connecting external resistance to adjust frequency is impossible. See "Frame-Frequency Adjustment Function" to adjust frame frequency. External resistance is not needed.
Open Open
OSC1 OSC2
R61505U
Figure 68 Note 1: OSC frequency is set at Typ.376kHz (R61505U0) or 600Khz (R61505U1) (See Electrical Characteristics).
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R61505U
Correction function
The R61505U supports -correction function to display in 262,144 colors simultaneously using gradientadjustment, amplitude-adjustment, fine-adjustment, tap-adjustment, and voltage division ratio adjustment registers. Each register consists of positive-polarity register and negative-polarity register to allow optimal gamma correction setting for the characteristics of the panel by enabling different settings for positive and negative polarities. Correction registers The -correction registers of the R61505U consists of gradient-adjustment, amplitude-adjustment, fineadjustment, tap-adjustment, and voltage division ratio adjustment registers to correct grayscale voltage levels according to the gamma characteristics of the liquid crystal panel. These register settings make adjustments to the relationship between grayscale number and grayscale voltage and the setting can be made differently for positive and negative polarities (the reference level and the register settings are the same for all RGB dots). The function of each register is as follows.
Grayscale voltage
Grayscale voltage
Grayscale number (Vx)
Grayscale number (Vx)
Grayscale voltage
Grayscale number (Vx)
Gradient adjustment
Amplitude adjustment
Fine adjustment
Grayscale voltage
Grayscale number (Vx)
Grayscale voltage
Grayscale number (Vx)
Tap adjustment
Voltage division ratio adjustment
Figure 69
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R61505U Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient, which represents the relationship between grayscale and voltage, without changing the dynamic range. The grayscale voltages for middle grayscale number can be adjusted by this register setting. Amplitude adjustment registers The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage. Fine adjustment registers The fine adjustment registers are used for minute adjustment of grayscale voltage levels. Tap adjustment registers The tap adjustment registers are for selecting two tap voltage supply points from V3 to V6 and from V25 to V28 by using selector. Voltage division ratio adjustment registers The voltage division ratio adjustment registers are used to change the division ratios between V0 and V1 and between V30 and V31. Table 85 correction registers
Register Gradient Amplitude Positive P0RP0 [2:0] P0RP1 [2:0] V0RP0 [4:0] V0RP1 [4:0] P0KP0 [2:0] P0KP1 [2:0] P0KP2 [2:0] P0KP3 [2:0] P0KP4 [2:0] P0KP5 [2:0] Fine adjustment P0FP0 [1:0] Negative P0RN1 [2:0] P0RN0 [2:0] V0RN1 [4:0] V0RN0 [4:0] P0KN5 [2:0] P0KN4 [2:0] P0KN3 [2:0] P0KN2 [2:0] P0KN1 [2:0] P0KN0 [2:0] P0FN3 [1:0] Function Grayscale V4 variable resistance Grayscale V27 variable resistance Voltage level for grayscale V0 Voltage level for grayscale V31 Voltage level for grayscale V1 Voltage level for grayscales V3, V4, V5, V6 Voltage level for grayscale V10 Voltage level for grayscale V21 Voltage level for grayscales V28, V27, V26, V25 Voltage level for grayscales V30 Division ratio between V0 and V1 P0FP1[1:0]: specify either one of grayscales V3, V4, V5, V6 for the P0KP1[2:0] level P0FN2[1:0]: specify either one of grayscales V3, V4, V5, V6 for the P0KN4[2:0] level P0FP2[1:0]: specify either one of grayscales V28, V27, V26, V25 for the P0KP4[2:0] level P0FN1[1:0]: specify either one of grayscales V28, V27, V26, V25 for the P0KN1[2:0] level Division ratio between V30 and V31
P0FP1 [1:0]
P0FN2 [1:0]
P0FP2 [1:0]
P0FN1 [1:0]
P0FP3 [1:0]
P0FN0 [1:0]
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R61505U Correction register settings and curve relationship
Gamma Correction Registers Function
V0 5'h00
REV = 0
V0RN1
5'h1F 3'h0
V2 2'h0
V0RP0 P0FN3
5'h1F
4
2'h3 2'h3 3'h7 2'h0 V6 3'h0
5'h00 V0
P0FN2 P0KN5
3'h7
P0RN1
V10 3'h7 3'h0
P0KP0
3'h7
P0KN4
3'h7
P0FP0
V21 3'h0 3'h0 2'h3 3'h0 V1 3'h7 2'h3 3'h7 2'h0
P0KN3 3
Grayscale voltage [V]
P0KN2
P0FN1 P0KN1
3'h7
3'h7
2'h3 3'h7
P0KP1 P0FP1
V3 2'h0
P0KP2
3'h0
P0RP0
V10 3'h0 2'h3 3'h0
P0KP3 2 P0KP4 P0KP5
3'h7 3'h7 3'h7 3'h0 3'h7
P0FN0
3'h7 V21
P0FP2
2'h3 2'h3 5'h1F 2'h0 V25 3'h0
P0KN0
V31
P0RP1 Positive polarity Negative polarity
5'h00
1
3'h0 2'h0
V0RN0
5'h1F
5'h00 V31
0 6'd0 6'd8 6'd16 6'd24 6'd32 RAM Data [dec] 6'd40 6'd48 6'd56 6'd63
Figure 70
Sn VCOM
Positive polarity Negative polarity
Figure 71 Source output waveform and VCOM polarity relationship
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R61505U
Power-supply Generating Circuit
The following figures show the configurations of liquid crystal drive voltage generating circuit of the R61505U. Power supply circuit connection example 1 (VCI1 = VCIOUT) In the following example, the VCIOUT level is adjusted internally in the VCIOUT output circuit.
(1) VREG1OUT (2) VREG 1 regulator Grayscalevoltage generation circuit S1-S720
VCILVL VCIOUT VCOMR (3) VCI1 C11(4) C11+ C12(5) (6) VCI (7) C12+ VLOUT1 DDVDH VCIOUT output circuit
Internal reference voltage generation circuit
Source driver
VCOMH Vcom level adjustment circuit VcomH, VcomL output circuit
(17)
Step-up circuit 1
VCOM
VCOML (18)
R61505U
G1-G320
C13(8) C13+ C21(9) C21+ C22(10) C22+ C23(11) DDVDH (12) (13)
see Note
Step-up circuit 2
VCC GND/RGND VCILVL
C23+ VLOUT2 VGH (14) VLOUT3 VGL (15)
see Note
R63400A0
VCI AGND IOVCC IOGND VDD (19)
VCL
(16)
Figure 72
Note: The wiring resistances between the schottky diode and GND/VGL must be 10 or less.
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R61505U Power supply circuit connection example 2 (VCI1 = VCI direct input) In the following example, the electrical potential VCI is directly applied to VCI1. In this case, the VCIOUT level cannot be adjusted internally but step-up operation becomes more effective.
(1) VREG1OUT (2) VREG 1 regulator Grayscalevoltage generation circuit S1-S720
VCILVL VCIOUT VcomR
see Note 2
VCIOUT output circuit
Internal reference voltage generation circuit
Source driver
Vci
(4)
VCI1 C11C11+ C12VcomH, VcomL output circuit
VcomH Vcom level adjustment circuit
(17)
Step-up circuit 1
Vcom
(5) (6) VCI (7)
C12+ VLOUT1 DDVDH
VcomL (18)
C13(8) C13+ C21(9) C21+ C22(10) C22+ C23(11) DDVDH (13)
see Note
R61505U
Step-up circuit 2
G1-G320
VCC GND/RGND VCILVL
C23+ VLOUT2 VGH (14) VLOUT3 VGL (15)
see Note
(12)
R63400A0
VCI AGND IOVCC IOGND
VCL VDD (16)
(19)
Figure 73
Notes: 1. The wiring resistances between the schottky diode and GND/VGL must be 10 or less. 2. When directly applying the VCI level to VCI1, set VC = 3'h7. Capacitor connection to VCIOUT is not necessary. Rev.1.21 April 9, 2007, page 159 of 205
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R61505U
Specifications of Power-supply Circuit External Elements
The specifications of external elements connected to the power-supply circuit of the R61505U are as follows. Table 86 Capacitor
Capacitance 1F (B characteristics) Notes: Voltage proof 6V 10 V 25 V Pin Connection (1) VREG1OUT, (3) VCIOUT, (4) C11-/+, (5) C12-/+, (8) C13-/+, (16) VCL, (17) VCOMH, (18) VCOML, (19) VDD (6) VLOUT1, (9) C21-/+, (10) C22-/+, (11) C23-/+ (11) VLOUT2, (13) VLOUT3
1. Check with the LC module. 2. The numbers in the parentheses corresponds to the numbers of the elements in Figure 72, Figure 73.
Table 87 Schottky Diode
Specification VF < 0.4 V/20 mA@25 C, VR 25 V (Recommended diode: HSC226) Pin Connection (15) GND-VGL, (13) DDVDH-VGH, (7) VCI-DDVDH
Table 88 Variable Resistor
Specification > 200 k Pin Connection (2) VCOMR
Table 89 Internal logic power supply
Capacitance 1F (B characteristics) Voltage proof (recommended) 3V Pin Connection VDD
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R61505U
Voltage Setting Pattern Diagram
The following are the diagrams of voltage generation in the R61505U and the TFT display application voltage waveforms and electrical potential relationship.
VLOUT2
VGH
BT
VLOUT1 BT VRH
VCILVL(2.5 ~ 3.3V)
DDVDH VREG1OUT VCM/VCOMR VCOMH
VREG1OUT
VC VCI1 VDV
VCC(2.5 ~ 3.3V)
IOVCC(1.65 ~ 3.3V)
GND(0V) VCOML
VCL
BT VLOUT3 VGL
Figure 74
Notes: 1. The DDVDH, VGH, VGL, and VCL output voltages will become lower than their theoretical levels (ideal voltages) due to current consumption at each output level. Make sure that output voltage level in operation maintains the following relationship: (DDVDH - VREG1OUT) 0.5V, (VCOML - VCL) > 0.5V. Also make sure VGH-VGL 28V, VCI-VCL 6V. When the alternating cycle of VCOM is high (e.g. polarity inverts every line cycle), current consumption will increase. In this case, check the voltage before use. 2. In operation, setting voltages within the respective voltage ranges are recommended.
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R61505U Liquid crystal application voltage waveform and electrical potential
VGH
VREG1OUT VCOMH VCOM VCOML
Sn (source driver output)
Gn (panel interface output)
Figure 75
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R61505U
VCOMH voltage adjustment sequence
When adjusting the VCOMH voltage by setting VCM1 [5:0] in the R29'h register (internal VCOMH level adjustment circuit), follow the sequence below. The R61505U can retain the VCOMH level adjustment setting values in NVM, which allows writing twice (only one setting value can be written in NVM at one time). In writing the setting value in NVM, write the VCOMH adjustment setting value VCM1 [4:0] in ED[4:0] and ED[7] = 0 when writing in NVM for the first time or ED[7] = 1 when writing for the second time. When writing the setting value in NVM, follow the NVM control sequence and NVM write sequence in the following pages.
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R61505U
Display ON sequence
VcomH adjustment R29h: VCM1[4:0]
Write the setting value in VCM1[4:0]
Write the setting value to adjust the VcomH level in VCM1[4:0]
Check the display quality
The display on the panle will flicker when the VcomH level is adjusted internally
Complete the VcomH level adjustment
When writing the VCOMH adjsutment setting value in NVM for the first time VCM1[4:0] (R29h)
Index IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5
29'h
0
0
0
0
0
0
0
0
0
0
0
IB4 IB3 IB2 IB1 IB0 VCM1 VCM1 VCM1 VCM1 VCM1 [4] [3] [2] [1] [0]
Write the setting value in VCM1[4:0] in ED[4:0]
NVM write register(A1'h)
Index IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8
A1'h
0
0
0
0
0
0
0
0
IB7 IB6 ED[7] 0 =0
IB5
0
IB4 ED [4]
IB3 ED [3]
IB2 ED [2]
IB1 ED [1]
IB0 ED [0]
When writing the VCOMH adjustment setting value in NVM for the second time VCM2[4:0] (R2Ah)
Index IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 VCM SEL IB6 IB5 IB4 IB3 IB2 IB1 IB0 VCM2 VCM2 VCM2 VCM2 VCM2 [4] [3] [2] [1] [0]
2A'h
0
0
0
0
0
0
0
0
0
0
Write the setting value in VCM2[4:0] in ED[4:0] and VCMSEL = 1 in ED[7] at the same time
NVM write register(A1'h)
Index IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8
A1'h
0
0
0
0
0
0
0
0
IB7 ED [7]
IB6
IB5
0
0
IB4 ED [4]
IB3 ED [3]
IB2 ED [2]
IB1 ED [1]
IB0 ED [0]
Figure 76
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R61505U
NVM control sequence
NVM write sequence
(VCC,VCI,IOVCC) ON VCI IOVCC1,2 VCC GND VCC IOVCC or VCC IOVCC
1ms or more
NVM load (register setting value rewrite) sequence
NVM dummy read RA0 (invalid data)
VCI VCI simultaneously
NVM Load RA4h: 16'h0001 (CALB = 1)
VPP1 = 9.0
0.1V 0.1V
8x 1/osc or more
VPP2 = 7.5
VPP3A/VPP3B=GND GND
1ms or more 1ms or more
NVM Load end (CALB = 0 automatically)
Power ON reset
2ms or more
Data transfer synchronization
RS=0, DB=16'h0000 RS=0, DB=16'h0000 RS=0, DB=16'h0000 RS=0, DB=16'h0000
NVM data read out R28: instruction read R29: instruction read R2A: instruction read
NVM dummy read
Instruction read (select one from RA0, RA1, or RA2) (Read data is invalid)
NVM write data setting RA1: 16'h00** ED = 8'hXX (arbitrary)
NVM data write start RA0:16'h0010 (TE=0,EOP=2'h1,EAD=2'h0)
NVM data write start RA0:16'h0090 (TE=1,EOP=2'h1,EAD=2'h0)
100~200ms
NVM data write end RA0:16'h0000 (TE=0,EOP=2'h0,EAD=2'h0)
1 s or more
NVM Write data in another address?
YES
NO VPP1 = 9.0 VPP2 = 7.5 0.1V 0.1V
VPP3A/VPP3B = GND
GND
1ms or more
Figure 77
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R61505U NVM Write In Sequence
NVM write-in Sequence
NVM data write start EAD[2:0] setting EOP[1:0]=2'h1 TE=1
Power ON reset
NVM write data setting ED7, ED[4:0]=0/1
NVM data write end EOP[1:0]=2'h0 TE=0
WR DB RESET*
INDEX ED [7:0] INDEX
TE, EOP, EAD [2:0]
INDEX
TE, EOP
Vcc/IOVcc VPP/1 (9.0V +/- 0.1V) VPP2 (7.5V+/- 0.1V)
GND GND GND GND GND open open
NVM write in period
1 ms or more each
2 ms or more
100~200 ms
1 s or more 1 ms or more
Figure 78
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R61505U NVM Read Out Sequence
NVM read out Sequence
NVM data read out CALB=1 NVM read out Read Instruction
Power ON reset
WR RD DB RESET*
INDEX CALB INDEX read NVM data
Vcc/IOVcc VPP1 (OPEN) VPP2 (OPEN)
GND
1ms or more
2ms or more
8 x 1/ osc
Figure 79
Written data on NVM can be confirmed by reading instruction registers. The write-in area is R28'h to R2A'h. Following table shows example of the reading out. Do not concern about ID7-5 (R29h) and ID6-5 (R2Ah) bits as individual die have different data. Check only the bits marked "user setting". Table 90
Index ID7 28'h ID6 ID5 ID4 ID3 ID2 ID1 ID0 To write in user ID
0 0 0 0 User User User User setting setting setting setting
To write in VCOM setting 29'h
* * * User User User User User setting setting setting setting setting
To write in VCOM setting 2A'h VCMSEL
* * User User User User User setting setting setting setting setting
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R61505U NVM instruction dummy read sequence
NVM dummy read RA0 (Invalid data)
NVM data read out 1 R28: Read instruction Dummy access is not required NVM data read out 2 R29: Read instruction Dummy access is not required NVM data read out 3 R2A: Read instruction
Read data bits in NVM (other than instruction data bits) Rxx: Read instruction Dummy access is required NVM dummy read RA0 (Invalid data)
NVM data read out 1 R28: Read instruction
Figure 80
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R61505U
Power supply Instruction Setting
The following are the sequences for setting power supply ON/OFF instructions. Set power supply ON/OFF instructions according to the following sequences in Display ON/OFF, Sleep set/exit sequences.
Power ON sequence
Power supply (Vcc, Vci, IOVcc) ON
Vci IOVcc Vcc GND Vcc IOVcc Vci or Vcc, IOVcc, Vci simultaneously
Power supply OFF sequence
Normal display
DTE = 1, D=2'h3, GON=1, VON = 1
Display OFF sequence
When registers are set: Powr supply OFF setting
Power supply Halt setting
R10h: AP = 3'h0, SAP=0 R11h: DC0=3'h6 R12h: PON = 0
1 frame or more
Power ON reset
2ms or more
DTE = 0, D=2'h0, GON=0 PON=0, VON=0
1) Source output: GND 2) Gate output: VCI 3) VCOM =GND
Transfer synchronization
RS=0, DB=16'h0000 RS=0, DB=16'h0000 RS=0, DB=16'h0000 RS=0, DB=16'h0000
Power supply Halt setting
R10h: APE=0
1) Source output: GND 2) Gate output: GND 3) VCOM =GND
RA4h: CALB=1
Wait 1/fosc x 8
Power supply (Vcc, Vci, IOVcc) OFF
User setting (1) Vci IOVcc Vcc GND Vci IOVcc Vcc or Vcc, IOVcc, Vci simultaneously
Initial instruction setting LCD Power supply ON sequence
R07h: D=2'h1 R17h: PSE=1'h1 R19h: TBT [1:0] = 2'h0
Set NL, BP, FP, Gamma, RTNI, DIVI others
Power supply user setting
R10h: APE = 1, AP, SAP=1, BT=3'h7 (Note 1) R11h: DC0, DC1, VC=3'h6 (Note 1) R12h: VRH, PON=1, VCMR=1(Note 2) R13h: VDV, R29h: VCM (Note 3) When registers are set: R12h: PSON=1'h1 1) Source output: GND 2) Gate output: VGH (all pins are ON) 3) VCOM =GND
Power supply startup time (8 frames x 1/OSC) Other mode setting instruction
Display ON sequence
Note 1: Set BT=3'h7 and VC=3'h6. Ultimate BT and VC settings are decided by user are set at "Power supply user setting" in the Display ON sequence. Note VC=3'h6 is inhibited to set when the electrical potential VCI is directly applied to VCI1 pin (connected on the substrate). Note 2: Set VCMR=1 when using internal electronic volume. Note 3: When NVM is in the status as the R61505U was shipped out, set R29h and R2Ah. If a user has finished writing in VCM1 and VCM2 settings to NVM, R29h and R2Ah are not required to be set.
Figure 81
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R61505U
Notes to Power Supply ON sequence
When voltages do not rise in the order of VCC, IOVCC and then VCI and have to change the order, please follow the following note. Note Internal operation of the R61505U is unstable until VCC rises. If IOVCC rose before VCC rises, the R61505U may be in "output" status. In this case, do not send or receive any data before power supply is completed. Changing order of voltage input will not cause troubles such as latchup or destruction of the LSI.
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R61505U
Instruction setting
The following are the sequences for various instruction settings. When setting instruction in the R61505U, follow the relevant sequence below. Display ON/OFF sequences
Display OFF sequence Display ON sequence
When registers are set:
Display OFF
LCD Power supply ON sequence* see Note
When registers are set:
2 frame periods or more
R07h: 16'h0072 (BASEE = 0, VON=1, GON=1, DTE=1, D=2'h2 )
Source output: non-lit display Gate output:VGH/ VGL VCOM =VCOMH / VCOML
Preparation for Display ON 1
R07h: 16'h0021 (BASEE = 0, VON=0, GON=1, DTE = 0, D=2'h1)
8H periods or more
Source output: GND Gate output: VGH (all pins are OFF) VCOM =GND
Display OFF
R07h: 16'h0001 (BASEE = 0, VON=0, GON=0, DTE=0, D=2'h1)
8H periods or more
Source output: GND Gate output: VGH (all pins are ON) VCOM =GND
Power supply user setting
R10h: BT R11h: VC
Display OFF
R07h: 16'h0000 (BASEE = 0 , VON=0, GON=0, DTE=0, D=2'h0)
Internal display operation halts. Source output: GND Gate output: VGH (all pins are ON) VCOM =GND
Preparation for Display ON 2
R07h: 16'h0061 (BASEE = 0, VON=1, GON=1, DTE = 0, D=2'h1)
2 frame periods or more
Source output: GND Gate output: VGL (all pins are OFF) VCOM =VCOMH / VCOML
LCD Power supply OFF sequence* see Note
Display ON
R07h: 16'h0173 (BASEE = 1, VON=1, GON=1, DTE = 1, D=2'h3)
Source output: V0-V31 Gate output:VGH/ VGL VCOM =VCOMH / VCOML
Display OFF
Display ON
Note: See power supply ON/OFF setting sequences
Figure 82
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R61505U Sleep mode SET/EXIT sequences
Sleep mode sequence
Display OFF sequence* see Note
Set Sleep mode
Sleep SET
R10h: SLP=1
Sleep EXIT
R10h: SLP=0
1clock or more
Exit Sleep mode
Display ON sequence* see Note
Figure 83
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R61505U Deep standby mode IN/EXIT sequences
18-/ 16-/ 9-/ 8 bit interface
Deep standby mode
Display off sequence
Set deep standby mode
Set deep standby mode
R10h: DSTB = 1
CS = low (1) CS = low (2)
1 ms or more
VDD startup oscillator stabilizing period
CS = low (3) CS = low (4) CS = low (5) CS = low (6)
Initialize the R61505U
Exit deep standby mode input CS = Low 6 times
RA4h: CALB = 1
1/fosc x 8 wait
Initial instruction setting RAM data setting
User setting 1 NL, BP, FP, gamma, RTNI, DIVI setting, others
Display on sequence
Notes: 1. See AC characteristics in "Electrical Characteristics" for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods. 2. Leave at least 1 ms between the 2nd and 3rd inputs of CS = Low. 3. This sequence must be completed before writing GRAM data.
CS WR RD RS
"High" "High"
1
2
Wait 1ms or more
3
4
5
6
"Low" or "High" Any data Any data Any data Any data Any data Any data
Data
Figure 84 Cancel standby mode by inputting CS="Low" (18-/ 16-/ 9-/ 8- bit interface)
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R61505U
18bit/16bit interface
Display off sequence
Set deep standby mode
Set deep standby mode R10h : DSTB=1
Index Write (Data=16'h0000) Index Write (Data=16'h0000)
1ms
VDD startup oscillator stabilizing period
Exit deep standby mode Initialize the R61505U
Index Write (Data=16'h0000) Index Write (Data=16'h0000) Index Write (Data=16'h0000) Index Write (Data=16'h0000)
R4Ah: CALB=1
1/fosc x 8 wait
Initial instruction setting RAM data setting
User setting 1 NL, BP, FP, gamma, RTNI, DIVI setting, others
Notes:
Display on sequence
1. See AC characteristics in "Electrical Characteristics" for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods. 2. Leave at least 1 ms between the 2nd and 3rd inputs of Index Write. 3. This sequence must be completed before writing GRAM data.
CS WR RD
1
2
Wait 1ms or more
3
4
5
6
"High" "Low"
RS Data
16'h0000
16'h0000
16'h0000
16'h0000
16'h0000
16'h0000
Figure 85 Cancel deep standby mode by inputting CS="Low" and WR="Low" (18-/ 16 bit interface)
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R61505U
9- /8- bit interface
Display off sequence
Set deep standby mode
Set deep standby mode R10h : DSTB=1
Index Write (Data=8'h00) Index Write (Data=8'h00)
1ms or more
VDD startup oscillator stabilizing period
Exit deep standby mode Initialize the R61505U
Index Write (Data=8'h00) Index Write (Data=8'h00) Index Write (Data=8'h00) Index Write (Data=8'hF0)
Index Write (Data=8'h00) Index Write (Data=8'h00) Index Write (Data=8'h00) Index Write (Data=8'h00)
Transfer synchronization command
Note 4
R4Ah: CALB=1
1/fosc x 8 wait
Initial instruction setting RAM data setting
User setting 1 NL, BP, FP, gamma, RTNI, DIVI setting, others
Notes:
Display on sequence
1. See AC characteristics in "Electrical Characteristics" for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods. 2. Leave at least 1 ms between the 2nd and 3rd inputs of Index Write. 3. This sequence must be completed before writing GRAM data. 4. Transfer synchronization command is 8'h00 when 8 bit interface is used and 9'h000 when 9 bit interface is used.
CS
1
2
Wait 1ms or more
3
4
5
6
1
2
3
4
WR
RD
"High" "Low"
RS Data
IW upper IW lower 00h 00h
IW upper IW lower IW upper IW lower 00h 00h 00h F0h
IW upper IW lower IW upper IW lower 00h 00h 00h 00h
transfer synchronization
Execute transfer synchronization command after canceling deep standby mode by inputting RS=Low and Index write.
Figure 86 Cancel deep standby mode by inputting CS="Low" and WR="Low" (9-/ 8- bit interface)
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R61505U 8-color mode setting
262,144 color to 8 color mode
262,144-color mode display
8 color to 262,144 color mode
8-color mode display
R07h: COL= 1'h1
R07h: COL= 1'h0
8-color mode display
262,144-color mode display
Figure 87 Partial display setting
Partial display setting sequence
Full-screen display
Partial display setting
R80h: PTDP0 R81h: PTSA0 R82h: PTEA0 R83h: PTDP1 R84h: PTSA1 R85h: PTEA1
Base image display OFF Partial display ON
R07h: BASEE=0, PTDEx=1
8-color display, low power consumption settings
R07h: COL=1, R09h: PTS Set as required
Partial display
Base image display ON Partial display OFF
R07h: BASEE=1, PTDEx=0
Full-screen display
Figure 88
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R61505U
Absolute Maximum Ratings
Table 91
Item Power Supply Voltage1 Power Supply Voltage 2 Power Supply Voltage 3 Power Supply Voltage4 Power Supply Voltage 5 Power Supply Voltage7 Power Supply Voltage 8 Power Supply Voltage 9 Power Supply Voltage 10 Power Supply Voltage 11 Input Voltage Operating Temperature NVM Write Temperature Storage Temperature
Symbol VCC, IOVCC VCI - AGND DDVDH - AGND AGND - VCL DDVDH - VCL AGND - VGL VGH- VGL VPP1 VPP2 VPP3A/VPP3B Vt Topr Twep Tstg V V V V V V V V V V V
Unit -0.3 +4.6 -0.3 +4.6 -0.3 +6.5 -0.3 +4.6 -0.3 +9.0
Value
Note 1, 2 1, 3 1, 4 1 1, 5 1, 6 1 1 1 1 1 1, 7 1 1
-0.3 +13.0 -0.3 +30.0 -0.3 +10.0 -0.3 +10.0 0 -0.3 IOVCC + 0.3 -40 +85 +25 +35 -55 +110

Notes 1.If the R61505U is used beyond the absolute maximum ratings, the LSI may be permanently damaged. It is strongly recommended to use the LSI under the condition within the electrical characteristics in normal operation. If exposed to the condition not within the electrical characteristics, it may affect the reliability of the device. 2. Make sure VCC(high)GND(low), IOVCC(high)IOGND(low) . 3. Make sure VCI(high)AGND(low) . 4. Make sure DDVDH(high)AGND(low). 5. Make sure DDVDH(high) VCL(low). 6. Make sure AGND(high)VGL(low). 7. The DC/AC characteristics of die and wafer products are guaranteed at 85.
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R61505U
Electrical Characteristics
DC characteristics (VCC= 2.50V~3.30VIOVCC=1.65V~3.30VTa=-40C~+85C Table 92
Item Input "High" level voltage Input "Low" level voltage Output "High" level voltage 1 (DB0-17, FMARK Output "Low" level voltage 1 (DB0-17, FMARK Input / Output leagage current Current Consumption ((IOVCCIOGND) + (VCC-GND)) Normal operation mode (260kcolor, display operation)
Symbol
See note 1)
Unit
Test Condition IOVCC=1.65V3.30V IOVCC=1.65V3.30V IOVCC=1.65V3.30V, IOH=-0.1mA IOVCC=1.65V3.30V, IOL=0.1mA Vin=0IOVCC fosc=376/600kHz (320 line drive), IOVCC=VCC=3.00V, fFLM=70Hz, Ta=25C, RAM data: 18'h000000, See below for other data fosc=376/600kHz (64 line partial display), IOVCC=VCC=3.00V, fFLM=40Hz, Ta=25C, RAM data: 18h'000000, See below for other data IOVCC=VCC=3.00V, Ta=25C IOVCC=2.40V, VCC=3.00V, tCYCW=125ns, Ta=25C, I80-8bit-I/F, TRIREG=1'h1, Consecutive RAM access during display operation, VCM1=5'h1D, AP=3'h3, BC0=0, FP=5, BP=8, register; 0(default), COL=0 (8-color mode)
Min. 0.80x IOVCC -0.3 0.8x IOVCC -1
Typ. 175 (376KHz) 190 (600Khz)
Max. IOVCC 0.20x IOVCC 0.20x IOVCC 1 295 (376KHz) 310 (600KHz)
Note
VIH VIL VOH VOL ILI
V V V V A
2,3 2,3 2 2 4
IOP1
A
5, 6
Current Consumption ((IOVCCIOGND) + (VCC-GND)) 8-color mode, 64-line partial display operation Current Consumption ((IOVCCIOGND) + (VCC-GND)) Deep Standby mode
Iop2
A
140
5, 6
IDST
A
0.1
1.0
5
Current Consumption ((IOVCCIOGND) + (VCC-GND)) RAM access mode 1 (Normal write operation, HWM=0)
IRAM1
mA
2.0
6
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R61505U
IOVCC=2.40V, VCC=3.00V, tCYCW=70ns, Ta=25C, I80-8bit-I/F, TRIREG=1'h1, Consecutive RAM access during display operation, VCM1=5'h1D, AP=3'h3, BC0=0, FP=5, BP=8, register; 0(default), COL=0 (8-color mode) IOVCC=VCC=3.00V, VCI=3.00V, fosc=376/600kHz (320 line), fFLM=70Hz, Ta=25C, RAM data: 18'h00000, REV="0", BC0=0, FP=5, BP=8, VxRPx="0", VxRNx="0", PxKPx="0", PxKNx="0", PxRPx="0", PxRNx="0", PxFPx="0", PxFNx="0", BT=3'h6, VC=3'h7, AP=3'h3, DC0=3'h1, DC1=3'h2, VRH=4'hA, VCM1=5'h1D, VDV=5'h8, VCMR=1'h1, COL=1'h0, GON=1, No load on the panel. IOVCC=VCC= 3.00V, VCI=3.00V, fosc=376/600kHz (64 line partial), fFLM=40Hz, Ta=25C, RAM data: 18'h00000, REV="0", BC0=0, FP=5, BP=8, VxRPx="0", VxRNx="0", PxKPx="0", PxKNx="0", PxRPx="0", PxRNx="0", PxFPx="0", PxFNx="0", BT=3'h6, VC=3'h7, AP=3'h3, DC0=3'h1, DC1=3'h2, VRH=4'hA, VCM1=5'h1D, VDV=5'h8, VCMR=1'h1, COL=1'h1, GON=1, No load on the panel.
Current Consumption ((IOVCCIOGND) + (VCC-GND)) RAM access mode 2, High-speed write function (HWM=1)
IRAM2
mA
1.7
6
LCD Power Supply Current (VCIGND) 260-k color display operation
1.4 (376KHz) 1.9 (600KHz)
3.0 (376KHz) 3.5 (600KHz) 5, 6
Ici1
mA
LCD Power Supply Current (VCIGND) 8-color (64-line partial) display operation
0.5 (376KHz) 0.8 (600KHz) 5, 6
Ici2
mA
Output voltage dispersion Average output voltage variance
VO V
mV mV
35
5
35
7 8
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R61505U Step-Up Circuit Characteristics Table 93
Item Step-up Output Voltage VLOUT1 V Unit Test Condition
IOVCC=VCC=3.00[V],VCI=VCI1=2.5[V], fosc=376/600[kHz],Ta=25C, VC=3'h7, AP=3'h3, BT=3'h7, DC0=3'h4div. 1/16, DC1=3'h4 (div. 1/ 256), COL=0, D=2'h0, VON=0, DIVI=2'h0, RTNI=5'h10, FP=4'h8, BP=4'h8, C11=C12=C13=C21=C22=C23=1[uF]/B Characteristics, VLOUT1=VLOUT2=VLOUT3=VCL=1[uF]/B Characteristics, No load on the panel, Iload1= -3 [mA] IOVCC=VCC=3.00[V],VCI=VCI1=2.5[V], fosc=376/600[kHz],Ta=25C, VC=3'h7, AP=3'h3, BT=3'h7, IOVCC=VCC=3.00[V],VCI=VCI1=2.5[V], fosc=376/600[kHz], Ta=25C, VC=3'h7, AP=3'h3, BT=3'h7, DC0=3'h4 (div. 1/16),
Min.
Typ.
Max.
Note
4.57
4.84
-
-
VLOUT2
V
DC1=3'h4 div. 1/256, COL=0, D=2'h0, VON=0, DIVI=2'h0, RTNI=5'h10, FP=4'h8, BP=4'h8, C11=C12=C13=C21=C22=C23=1[uF]/B Characteristics, VLOUT1=VLOUT2=VLOUT3=VCL=1[uF]/B Characteristics, Iload2=-100[uA], No load on the panel. IOVCC=VCC=3.00[V],VCI=VCI1=2.5[V], fosc=376/600[kHz], Ta=25C, VC=3'h7, AP=3'h3, BT=3'h7, DC0=3'h4 (div. 1/ 16), DC1=3'h4 div. 1/ 256, COL=0, D=2'h0, VON=0,
13.72
14.40
-
-
VLOUT3
V
DIVI=2'h0, RTNI=5'h10, FP=4'h8, BP=4'h8, C11=C12=C13=C21=C22=C23=1[uF]/B Characteristics, VLOUT1=VLOUT2=VLOUT3=VCL=1[uF]/B Characteristics, Iload3=+100[uA], No load on the panel. IOVCC=VCC=3.00[V], VCI=VCI1=2.5[V], fosc=376/600[kHz], Ta=25C, VC=3'h7, AP=3'h3, BT=3'h7, DC0=3'h4 (div. 1/16), DC1=3'h4 (div. 1/ 256), COL=0,
-6.86
-7.13
-
-
VCL
V
D=2'h0, VON=0, DIVI=2'h0, RTNI=5'h10, FP=4'h8, BP=4'h8, C11=C12=C13=C21=C22=C23=1[uF]/B Characteristics, VLOUT1=VLOUT2=VLOUT3=VCL=1[uF]/B Characteristics, Iload4=+200[uA], No load on the panel.
-2.25
-2.30
-
-
Input Voltage
VCI
V
2.5
-
3.3
-
Internal Reference Voltage (Condition: VCC= 2.50V3.30V, Ta=25) Table 94
Item Internal Reference Voltage Symbol VCIR Unit V Min. 2.45 Typ. 2.50 Max. 2.55 Note 12
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R61505U AC Characteristics (VCC= 2.50V3.30VIOVCC=1.65V3.30VTa=-40C+85C See Note 1) 1. Clock Characteristics Table 95
Item RC oscillation clock (R61505U0) RC oscillation clock (R61505U1) Symb ol fosc fosc Unit kHz kHz Test Condition
IOVCC=VCC=3.0V 25
Min. 349 558
Typ. 376 600
Max. 402 642
Note 9 9
IOVCC=VCC=3.0V 25
2. 80-System Bus Interface Timing Characteristics (18-/ 16- bit interface) Table 96 Normal write operation (HWM=0), IOVCC=1.65V~3.30V
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write / Read rise/ fall time Setup time Write (RS to CS* WR*) Read (RS to CS*RD*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time tAH tDSW tH tDDR tDHR Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr
WRf
Unit ns ns ns ns ns ns ns ns
Timing Diagram Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97
Min. 125 450 45 170 70 250
Typ.
Max. 25
0 10 2 25 10 5
tAS ns ns ns ns ns ns 150
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R61505U Table 97 High-speed write Function (HWM=1), IOVCC=1.65~3.30V
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write / Read rise/ fall time Setup time Write (RS to CS* WR*) Read (RS to CS*RD*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time tAH tDSW tH tDDR tDHR Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr
WRf
Unit ns ns ns ns ns ns ns ns
Timing Diagram Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97
Min. 75 450 40 170 25 250
Typ.
Max. 25
0 10 2 25 10 5
tAS ns ns ns ns ns ns 150
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R61505U 3. 80-System Bus Interface Timing Characteristics (9-/ 8- bit interface) Table 98 Normal Write Function (HWM=0)/ High-speed Write Function (HWM=1), IOVCC=1.65~3.30V)
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write / Read rise/ fall time Setup time Write (RS to CS* WR*) Read (RS to CS*RD*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time
Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr
WRf
Unit ns ns ns ns ns ns ns ns
Timing Diagram Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97 Figure 97
Min. 70 450 30 170 25 250
Typ.
Max. 25
0 10 2 25 10 5
tAS ns tAH tDSW tH tDDR tDHR ns ns ns ns ns 150
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R61505U 4. Clock-synchronized Serial Interface Timing Characteristics Table 99 Normal Write Function (HWM=0), High-speed Write Function (HWM=1), IOVCC=1.65~3.30V)
Item Serial clock cycle time Serial clock highlevel width Serial clock lowlevel width Write (receive) Read (transmitted) Write (receive) Read (transmitted) Write (receive) Read (transmitted) Symbol tSCYC tSCYC tSCH tSCH tSCL tSCL tSCrtSCf tCSU tCH tSISU tSIH tSOD tSOH Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Timign Diagram Figure 98 Figure 98 Figure 98 Figure 98 Figure 98 Figure 98 Figure 98 Figure 98 Figure 98 Figure 98 Figure 98 Figure 98 Figure 98 Min. 100 350 40 150 40 150 20 60 30 30 5 Typ. Max. 20,000 20,000 20 130
Serial clock rise/fall time Chip select setup time Chip select hold time Serial input data setup time Serial input data hold time Serial output data delay time Serial output data hold time
5. Reset Timing Characteristics (IOVCC=1.65~3.30V) Table 100
Item Reset low-level width Reset rise time Symbol tRES trRES Unit ms s Timign Diagram Figure 99 Figure 99 Min. 1 Typ. Max. 10
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R61505U 6. RGB Interface Timing Characteristics Table 101 18-/ 16- bit RGB interface (HWM=1), IOVCC=1.65~3.30V
Item VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time DOTCLK low-level pulse width DOTCLK high-level pulse width DOTCLK cycle time Data setup time Data hold time DOTCLK, VSYNC and HSYNC rise/fall time Symbol tSYNCS tENS tENH PWDL PWDH tCYCD tPDS tPDH trgbr trgbf Unit clock ns ns ns ns ns ns ns ns Timign Diagram Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Min. 0 10 20 40 40 100 10 40 Typ. Max. 1 25
Table 102 6-bit RGB interface (HWM=1), IOVCC=1.65~3.30V
Item VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time DOTCLK low-level pulse width DOTCLK high-level pulse width DOTCLK cycle time Data setup time Data hold time DOTCLK, VSYNC and HSYNC rise/fall time Symbol tSYNCS tENS tENH PWDL PWDH tCYCD tPDS tPDH trgbr trgbf Unit clock ns ns ns ns ns ns ns ns Timign Diagram Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Figure 100 Min. 0 10 25 25 25 60 10 25 Typ. Max. 1 25
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R61505U 7. LCD driver Output Characteristics Table 103
Item Symbol Unit Timing Diagram
VCC=IOVCC=3.00V, DDVDH=5.50V, VREG1OUT=5.00V, fosc=376/600kHz (320-line drive), Ta=25C, REV=0, AP=3'h3, VRH=4'h0, PxKPx=3'h0, PxKNx=3'h0, PxRNx=3'h0, PxRPx=3'h0,
Min.
Typ.
Max.
Note
Source driver output delay time
tdds
s
VxRNx=5'h0, VxRPx=5'h0, PxFPx=2'h0, PxFNx=2'h0 Same change from same grayscale at all time-division source output pins. Time to reach +/- 35mV from VCOM polarity inversion timing.. R=10kohm, C=20pF VCC=IOVCC=3.00V, DDVDH=5.50V, VREG1OUT=5.00V, fosc=376/600kHz (320 line drive), Ta=25C, REV=0, AP=3'h3, VRH=4'h0, PxKPx=3'h0, PxKNx=3'h0,
17
10
VCOM output delay time
tddv
s
PxRNx=3'h0, PxRPx=3'h0, VxRNx=5'h0, VxRPx=5'h0, PxFPx=2'h0, PxFNx=2'h0 Time to reach +/- 35mV when voltage on 0-V31 pins changes. R=100ohm, C=10nF
17
11
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R61505U Notes on Electrical Characteristics 1. 2. DC/AC electrical characteristics of bare die and wafer products are guaranteed at +85. The followings illustrate the configurations of input, I/O, and output pins.
Pins: FMARK, SDO
Pins: RESET* IM3-1 IM0/ID VSYNC HSYNC DOTCLK ENABLE CS, RS, SDI IOVCC
IOVCC
PMOS Input circuit NMOS Input data
PMOS NMOS
IOGND
IOGND
Pins: WR/SCL RD IOVCC
PMOS PMOS Input circuit
Input enable (CS)
NMOS
NMOS
IOGND Pins: DB17 - DB0 IOVCC
PMOS PMOS Input circuit
Input enable(CS)
NMOS
NMOS
IOGND Output circle; Three states IOVCC Output enable PMOS NMOS Output data
IOGND
Figure 89
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R61505U 3. 4. 5. Fix pins as follows; TEST1/2/5 pins to IOGND, TEST3/4 pins to IOVCC, VDDTEST and VREFC to ground (AGND), and IM0/ID pins to IOVCC or IOGND. This excludes the current in the output-drive MOS. This excludes the current in the input/output units. Make sure that the input level is fixed because through current will increase in the input circuit when the CMOS input level takes a middle range level. The current consumption is unaffected by whether the CS* pin is "high" or "low" while not accessing via interface pins. The relation between voltage and current consumption is as follows.
6.
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R61505U
Current consumption in normal display operation (262k-color display mode)
262k color-mode fosc=600KHz
200
Typ. fosc=376KHz
320 line Ta=25 , fosc=376/600 kHz, fHLM=70Hz, RAM data=18'h00000 COL=0
Iop1 uA
150
100
2.5
3.0 IOVCC/VCC V
3.5
Current Consumption in normal display operation (8-color-mode, 64 line partial display)
320 line Ta=25 , fosc=376/600kHz, RAM data =18'h00000 COL=1, 8-color-mode, 64 line partial display 200
8color-mode 64line partial display
Iop2 uA
150
Typ.
100
2.5
3.0 IOVCC/VCC V
3.5
Dynamic current consumption (RAM write during display RAM access) 8.0 IOVCC=2.4V, VCC=3.0V Ta=25 , fosc=376/600kHz
6.0
IRAM1, IRAM2 mA
18/16bitI/F HWM=0 4.0 Typ.
IRAM1 8bitI/F HWM=0 Typ. 18/16bitI/F HWM=1 Typ.
2.0 8bitI/F HWM=1 Typ. IRAM2
0.0 5.0 10.0 Write cycle fequency[MHz] 15.0
Figure 90
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R61505U
Liquid crystal power supply current consumption in 262k-color-mode (Ici1)
262k color mode IOVCC=VCC=3V, 320line, Ta=25C, fosc=376/600kHz, fFLM=70Hz, RAM data=18'00000, BC0=1'h0, REV=1'h0, COL=2'h0, AP=3'h3, BT=3'h5, DC0=3'h1, DC1=3'h2, VCMR=1'h1, VC=3'h7, VRH=4'hA, VCM=5'h1D, VDV=5'h8, GON=1 PxKPx=3'h0, PxKNx=3'h0, PxRNx=3'h0, PxRPx=3'h0, VxRNx=3'h0, VxRPx=3'h0, PxFNx=2'h0, PxFPx=2'h0, No load on the panel.
2.0
fosc=600KHz
Ici1 mA
1.5
fosc=376KHz Typ.
1.0
2.5
3.0 VCI V
3.5
Liiquid crystal power supply current consumption (Ici2) in 8-color, 64-line partial, display
IOVCC=VCC=3V, 320line, Ta=25C, fosc=376/600kHz, fFLM=40Hz, RAM data=18'00000, BC0=1'h0, REV=1'h0, COL=2'h1, AP=3'h3, BT=3'h5, DC0=3'h1, DC1=3'h2, VCMR=1'h1, VC=3'h7, VRH=4'hA, VCM=5'h1D, VDV=5'h8, GON=1 8 color mode 64line partial display PxKPx=3'h0, PxKNx=3'h0, PxRNx=3'h0, PxRPx=3'h0, VxRNx=3'h0, VxRPx=3'h0, PxFNx=2'h0, PxFPx=2'h0, No load on the panel.
fosc=600KHz
0.7
Ici2 mA
0.5
Typ. fosc=376KHz
0.3
2.5
3.0 VCI V
3.5
Figure 91
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R61505U 7. 8 The output voltage deviation is the difference in the voltages between output pins that are placed side by side in same display mode. The output voltage deviation is reference value. The average output voltage dispersion is the variance of average source-output voltage of different chips of the same product. The average source output voltage is measured for one chip with same display data. This applies to internal oscillators when using an internal RC oscillator.
9
10 The liquid crystal driver output delay time depends on the load on the liquid crystal panel. Adjust the frame frequency and the cycle per line by checking the quality on the actual panel in use.
Reference data
VCC=IOVCC=3.00V, DDVDH=5.50V, VREG1OUT=5.00V, fosc=376/600kHz (320 line drive) Ta=25 , REV=0, AP=2'h3, VRH=4'h0, PxKPx=3'h0, PxKNx=3'h0, PxRNx=3'h0, PxRPx=3'h0, VxRNx=3'h0, VxRPx=3'h0, PxFNx=3'h0, PxFPx=3'h0, Same change from the same grayscale at all time-division source output pins. Typ. Time to reach the target voltage inversion timing. R=10k, C=20pF 5mV from Vcom polarity
LCD driver output delay time tdds (s)
28 24 20 16 12 8 4 15 25 35
Load capacitance C (pF)
Figure 92
Rev.1.21 April 9, 2007, page 191 of 205
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R61505U 11 VCOM output delay time depends on the load on the liquid crystal panel. Adjust the frame frequency and the cycle per line checking the quality on the actual panel in use.
Reference data
Vcom output delay time: tDDv (s)
40 35 30 25
Typ.
20 15 10 10 30 50
VCC=IOVCC=3.00V, DDVH=5.50V, VREG1OUT=5.00V, fosc=376/600kHz(320 line drive) Ta=25 , REV=0, AP=2'h3, VRH=4'h0, PxKPx=3'h0, PxKNx=3'h0, PxRNx=3'h0, PxRPx=3'h0, VxRNx=5'h0, VxRPx=5'h0, PxFPx=2'h0, PxFNx=2'h0, Time to reach 35mV when voltage on Vo=V31 pin changes. R=100, C=10nF
Load capacitance C(nF)
Figure 93
12 Internal reference voltage VCIR depends on temperature as shown in following graph.
Reference Voltage
Internal reference voltage VCIR (V)
2.60
VCC=IOVCC=VCI=3.00V AP=2'h3
2.55
Typ.
2.50
2.45
2.40 -50 -30 -10
10 30
50
70
90
Temperature (C)
Figure 94
Rev.1.21 April 9, 2007, page 192 of 205
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R61505U Test Circuits
Test circuit for AC characteristics Test circuit for LCD output characteristics
[Data bus: DB17-DB0] Test Point
[LCD output: S1-S720] Load resistance R: 10k Test Point Load capacitance C:20pF
50pF
Figure 95
Test circuit for Vcom output characteristics [Vcom output] Test Point Load Capacitance C 10nF
Load Resictance R: 100
Figure 96
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R61505U
Test Characteristics
80-System Bus Interface
RS
VIH VIL tAS VIH VIL See Note 1) PWLW,PWLR VIH VIL tAH
VIH VIL
CS*
PWHW,PWHR VIH VIH tWRr
WR * RD* RD tWRf
VIH VIL
VIL
tCYCW, tCYCR
tDSW See Note 2) DB17-0 tDDR VIH VIL Write data
tH VIH VIL tDHR
See Note 2) DB17-0
VOH VOL
Read data
VOH VOL
Note 1) PWLW and PWLR are defined by the overlap period when CS* is "Low" and WR* or RD* is "Low". Note 2) Unused DB pins must be fixed at "IOVcc 1" or "IOGND 1".
Figure 97 80-System Bus Interface
Rev.1.21 April 9, 2007, page 194 of 205
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R61505U Clock Synchronous Serial Interface
End: P
Start: S
VIH
CS*
VIL
tSCYC tscr tCSU
VIH
tscf tSCH
VIH VIH VIL VIL
tSCL
tCH
VIH
SCL
VIL
VIL
tSISU
VIH
tSISH
VIH
SDI
Input data
VIL VIL
Input data tSOH
tSOD
VOH VOH
SDO
Output data
VOL
Output data
VOL
Figure 98 Clock Synchronous Serial Interface
Reset Operation
trRES
VIH VIL VIL
tRES RESET*
Figure 99 Reset Operation
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R61505U RGB Interface
trgbf trgbr
tSYNCS
VIH VIL VIH VIL
VSYNC HSYNC
tENS
tENH
VIH VIL
ENABLE
VIH VIL
trgbf PWDL
VIH VIL
trgbr PWDH
VIH VIL VIH VIL
DOTCLK
tCYCD tPDS
VIH
tPDH
VIH
DB17-0
VIL
Write data
VIL
Figure 100 RGB Interface
LCD Driver Output
tDDv VCOM
Target Voltage 35mV 35mV
Target Voltage
35mV
tDDs S1-720
Target Voltage
Target Voltage
35mV
Figure 101 LCD Driver Outputs
Rev.1.21 April 9, 2007, page 196 of 205
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R61505U
Revision Record
Rev. 0.04 0.1.0 0.10 Date 2005.01.26 2006.02.20 2006.04. 03 Contents of Modification First issue Change PAD Arrangement, add Instruction List. p.44 NW bit added (R02h) p. 53 PTG[1:0] 2'h1 changed to setting inhibited. p.59 VCL added to note 2 and 3. p.61 Setting of VREG1OUT added to Table 40. p.62 Description of VREG1 bit added. p.63 "5.5V or less" changed to "6.0V or less". (Note1 to Table 42) p.76 Table 51 6'h15 of NL[5:0] bits changed to 176 lines. p.81 VEQWI[1:0] bit added. p.85 EAD[1:0] bits added. p.86 Description of RA4h added. p.143 Description of line inversion AC drive added. p.149 (TBD)kHz changed to 376kHz. p.155 Table to Internal Oscillator deleted. p.161 Figure 78 added. p.163 "RF9h" deleted from Figure 80. p.166 "RF9h" deleted from Figure 83. pp.168-187 added. 0.11 0.12 2006. 05. 12 2006.05.31 p.169, pp.172-177 Target speculation value filled in (except Step-up circuit output characteristics) p.7 Change VCOM adjustment bits (11 bits 5 bits x 2 sets). p.8 Add VPP and delete note. p.15 Change the description of OSC1 and OSC2. p.17 Change the description of capacitor connection pins (C23). p.18 3.0V 4.0V (VREG1OUT) p.50 Change the table about VON. p.59 Add C13 (4'h1, 4'h4, 4'h6, 4'h9, 4'hC, and 4'hE) ,and delete C23 (4'h0 and 4'h8). p.62 VCM bits VCM1 and VCM2 bits p.88 Delete Status Read. p.89 Change the initial state of VLOUT1 and VLOUT2, add VCI1, and delete the initial state of C21+, C22+, and C23 p.157 2.5V 4.0V (VREG1OUT), (DDVDH - Drawn by
Approved by
Rev.1.21 April 9, 2007, page 198 of 205
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R61505U
Rev. Date Contents of Modification VREG1OUT) > 0.5V (DDVDH - VREG1OUT) 0.5V p.161 Change VPP1 and VPP2, and the description of dummy data read and write data setting. p.164 Add notes. p.169 Delete Power Supply Voltage 6, and add Power Supply Voltage 8 to 11, and NVM write temperature. p.173 Change timing diagram of clock characteristics. p.175 80ns 70ns (tCYCW), 50ns 38ns (PWLW) p.178 Delete Typ., and add Max (tdds and tddv). 0.13 2006.06.01 p.9 Delete C23 from R61505U's capacitor connection pins. p.16 Change note 2, VPP2 value, "When not in use" of VPP1, VPP2, and VPP3. 0.14 2006.06.02 p.9 Add VCL in R61505's capacitor connection pins, and change the description of R61505U's capacitor connection pins. p.18 Add "(VCILVL or VCIR)" in VREG1OUT. p.60 Change capacitor connection pins and VGL (max.), and add note 4. 0.15 2006.07.18 p.7 Gate drive power supply: VGH-GND=10.0V~15.0V VGH-GND=10.0V~20.0V, VGL-GND= -4.5V ~ -12.5V VGL-GND= -4.5V ~ -13.5V p.8 Add "Internal reference voltage: to generate VREG1OUT (VCIR)". p.9 Table 1: NVM_FUSE NVM, VGH 10.0V~15.0V 10.0V ~ 20.0V VGL -4.5V~ -12.5V -4.5V ~ -13.5V p.14 Change description to oscillator (8). VDH DDVDH (liquid crystal drive circuit power supply circuit, 9) p.17 Open Open or GND (VPP3: "When not in use" and NVM read) p.18 Add "Make sure to connect to stabilizing capacitor" to VCIOUT, VLOUT1, VLOUT2, VLOUT3 and VCL. p.19 Delete VDH from description of VREG1OUT. Add "Make sure to connect to stabilizing capacitor." to VCOMH and VCOML. p.21 TEST5 Delete " To stop the NVM operation, set the TEST5 pin to IOVCC level. p.61 VGH =15.0V (max.) 20.0V (max) VGL = -12.5V (max) -13.5V(max) p. 65 Error correction. (Description to VDV and Table 43) p.115 FPP + BPP = 16 FPP + BPP 16 p.159 Figure 74: VGH 10.0V~15.0V 10.0V ~ 20.0V, Drawn by
Approved by
Rev.1.21 April 9, 2007, page 199 of 205
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R61505U
Rev. Date Contents of Modification VGL -4.5V~ -12.5V -4.5V ~ -13.5V p.162 29'h 2A'h p.165 Figure 79: Error correction (Dummy access required Dummy access is not required.) p.166 Figure 80: Add CALB=1. p.167 Figure 81: Error correction. p.171 Table 88: -0.3 ~ +13.0 -0.3 14.0 (Power supply voltage 7) p.172 Table 89: Delete ""(Other than OSC1 pin)" (Input High level voltage, Input Low level voltage). VOH1 VOH, VOL1 VOL. p. 175 Change AC characteristics (Table 93: tcycw 150ns 125ns, PWLW 50ns 45ns. p.176 Change AC characteristics (Table 94: tcycw 80ns 75ns, PWLW 50ns 40ns). p.177 Change AC characteristics (Table 95: PWLW 38ns 30ns). p.181 Figure 86: Delete "DB17-0 (RGB interface (RM=1)) and "(80-system interface (RM=0))" p.187 Figure 91: "Data bus DB15-DB0" "Data bus DB17-DB0" p.188 Figure 93: tWRr tWRf, VIH VOH, VIL VOL. p.189 Figure 94: VOH1, VOL1 VOH, VOL p.190 Figure 97: S1-240 S1-720 0.1.6 2006.07.26 p.11 Figure 1: Change direction of arrow (VREG1OUT). p. 21 AGND IOGND (TSC) p.44 Delete row of "W" (R00h) p.50 Table 20: Source Output (S1-240) Source Output (S1-720). p.51 Table 23: VCOML GND p.57 9'h175 9'h15A, 9'h176 9'h15B, 9'h177 9'h1FF, 373rd line 346 line, 374th line 347th line, 375th line Setting disabled. p.91 Delete "Oscillator: Oscillate". p.142 Table 82: Delete row of "Write mask function". p.149 Figure 65: 8'h000, 8'h013 9'h000, 9'h013 (Partial image 1 display RAM area), PTDP0=8'h028 PTDP0=9'h028. p.152 Description changed. p.159 Figure 74: Delete voltage ranges. p. 170 Figure 84: R07h: COL=2'h1 COL=1'h1, COL=2'h0 COL=1'h0 Drawn by
Approved by
Rev.1.21 April 9, 2007, page 200 of 205
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R61505U
Rev. Date Contents of Modification p. 172 Table 89: AP=3'h3 AP=2'h3 (Current consumption, RAM access mode 1) p.173 AP=3'h3 AP=2'h3 (Current consumption, RAM access mode 2). AP=3'h3 AP=2'h3, COL=2'h0 COL=1'h0 (LCD Power Supply Current, 262-k color display operation). AP=3'h3 AP=2'h3, COL=2'h1 COL=1'h1 (LCD Power Supply Current, 8 color display operation). p.181 Figure 86: Change wiring. p.185 Figure 89: AP=3'h1 AP=2'h3 p.186 Figure 90: AP=3'h1 AP=2'h3 p.187 Figure 90: Load capacitance C25pF 20pF 1.0 2006.09.13. p.8 Add product numbers. p.17 Delete Note 1 to VPP. p. 18 Error correction (VLOUT2= max, 15.0 20.0V, VLOUT3=min. -12.5 -13.5V) p.50 Revise description of COL. p. 53 Table 26 Error correction. p. 57 Table 33 Error correction (FMP). p. 83 Delete VEQWI (R93h). p. 84 Error correction (Instruction List, R95h). p. 88 Change description of CALB. p. 90 Change Instruction List (Delete VEQWI, R93h). p. 108 Table 68 "11" Read instruction or RAM data Read register settings or RAM data. p. 109 Figure 28 Delete "(d) Instruction Read". p. 120 Figure 38 Error correction. p. 152 Revise description of "Oscillator". p. 163 Revise Figure 77. p. 165 Inserted. p. 166 Figure 80: Error correction (NVM dummy read). p. 167 Revise Figure 81. p. 168 Insert "Notes on Power Supply ON sequence". p. 169 Revise Figure 83 (Display ON/OFF sequence). p. 171 Revise Figure 85 (Deep standby mode). p.172 Insert Figure 86 (Deep standby mode). p. 173 Insert Figure 87 (Deep standby mode). pp. 176-184 Revise Electrical characteristics. pp. 187-190 Graphs inserted. p. 190 Add Note 12 Drawn by
Approved by
Rev.1.21 April 9, 2007, page 201 of 205
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R61505U
Rev. 1.1 Date 2006/11/15 Contents of Modification p. 58 Insert R0Eh VCOM Low Power Control. p. 84 Add VEQWI (R93h). p.88 Change description of EOP (delete "and store write-in data to register). p. 89 Change description to CALB. p. 90 Delete R0E from setting disabled instructions. p.112 Calculation Example Frame frequency 60Hz 65Hz Internal clock frequency (fosc) [Hz] = 60 Hz x (320 + 2 + 14) lines x 16 clocks x 1.1 / 0.9 = 394 kHz Internal clock frequency (fosc) [Hz] = 65 Hz x (320 + 2 + 14) lines x 16 clocks x 1.07 / 0.93 = 402 kHz Minimum speed for RAM writing [Hz] > 240x320/ {((14+320-2)lines x 16 clocks) x 1/394kHz = 5.7MHz 240x320/ {((14+320-2)lines x 16 clocks) x 1/402kHz = 5.81MHz p. 113 Figure 31 (graph) RAM write 5.7MHz 5.81MHz RC oscillation 10% 7% 16.67 (60MHz) 15.38 (65Hz) Figure 32 (graph) RAM write 5.7MHz 5.81MHz RC oscillation 10% 7% 16.67 (60MHz) 15.38 (65Hz) p. 139 Calculation Example Frame frequency 60Hz 65Hz Internal clock frequency (fosc) =60Hz x (320+2+14)lines x 16 clocks x 1.1/0.9 =349kHz 65Hz x (320+2+14)lines x 16 clocks x 1.07/0.93 =402kHz Minimum speed for RAM writing [Hz] > 240 x 320 / {((2+14 + 320- 2)lines x 16 clocks) x 1/ 394kHz} = 5.67MHz 240 x 320 / {((2+14 + 320- 2)lines x 16 clocks) x 1/ 402kHz} = 5.81MHz Figure 55 (graph) RAM write 5.67MHz 5.81MHz RC oscillation 10% 7% RAM write 5.67MHz 5.81MHz 13.54, 13.64 13.22 16.67 (60Hz) 15.38(65Hz) p. 144 Window address area setting range Horizontal direction 8'00 HSAHEA8'hEF 8'00 HSAApproved by
Rev.1.21 April 9, 2007, page 202 of 205
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R61505U
Rev. Date Contents of Modification p. 188 Figure 90 Change label on x-axis. p. 190 Figure 92 Error correction (tDD on y-axis tdds) 1.21 2007/04/09 p. 6 Description: "As moving picture interface" deleted. "Also, the R61505U incorporates step-up circuit and voltage follower circuit to generate TFT liquid crystal panel drive voltages." "The power supply circuit incorporates step-up circuit and voltage follower circuit to generate TFT liquid crystal panel drive voltages." p. 8 Product Number: Oscillation Frequency Oscillation Frequency p. 9 Table 1: VPP3: GND p. 10 Table 2, 3 BT[3:0] p. 11 Figure 1: 8bit serial interface) BT[2:0], 4'h0 RC Drawn by
Approved by
VPP3A/ VPP3B: GND 3'h0 8bit, Serial (System
p. 13 External Display Interface (RGB, VSYNC interface) "The R61505U allows switching interface by instruction according to the display, i.e. still and/or moving picture(s). The R61505U writes all display data via RGB interface to the internal GRAM in order to transfer data only when updating the data and thereby reduce the data transfer and power consumption for moving picture display." "The R61505U allows switching interface by instruction according to the display, i.e. still and/or moving picture(s) in order to transfer data only when the data is updated and thereby reduce the data transfer and power consumption for moving picture display." p. 14 OSC: "Internal RC oscillator generates clock signal used to operate the R61505U." "The R61505U generates the RC oscillation clock using internal RC oscillator." p. 17 Table 11: VPP3 VPP3A/VPP3B, Open or GND GND (VPP3A/VPP3B, EEPROM read), when not used: Open or GND GND pp.24-38 Pad coordinates: Rev. 0.1 No. 23 PROTECT TEST3 Rev. 1.2.p. 24
p. 43 l.2 "The R61505U starts internal processing after storing control information of externally sent data (16, 8, 1 bit(s)) in the instruction register (IR) and the data register (DR)." "The R61505U starts internal processing after storing control information (16, 8, 1 bit(s)), sent from the microcomputer, in the instruction register (IR) and the data register (DR)." "When accessing the R61505U's internal RAM, data is processed in units of 18 bits" deleted. p. 45 NW bit: "When BC=1" "When line inversion waveform is selected (BC0=1)"
Rev.1.21 April 9, 2007, page 203 of 205
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R61505U
Rev. Date Contents of Modification BC bit "BC=0, BC=1" correction) p. 60 AP[1:0] p. 61 BT[3:0] added. "BC=0, BC0=1" (Error Drawn by
Approved by
p. 48 Figure 3, 4: Revised. AP[2:0], Table 35 changed. BT[2:0], Table 37 changed. SAP[1:0]
p. 62 Note 2 to Table 38 added. Note to Table 39 deleted. p. 63 Table 40, VC bit setting: 3'h2 Setting inhibited 0.84 x VCILVL, 3'h4 0.76 x VCILVL Setting inhibited, 3'h6 Setting inhibited 0.7 x VCILVL. Added Note 3, 4 to Table 40. p. 66 Description to PSE=0 deleted. p. 67 Power Control 6: R19h inserted. p. 70 Note to Table 46: (Vn+Vn+1)/2, (Vn+2Vn+1)/3 (Vn+Vn+1)/2, (V1+2V0)/3 and (V30+2V31)/3 p. 71 Note to Table 71: (Vn+Vn+1)/2, (Vn+2Vn+1)/3 (Vn+Vn+1)/2, (V1+2V0)/3 and (V30+2V31)/3 p. 72 " the first word read immediately after RAM address set is executed is taken in the internal readdata latch and invalid data is sent to the data bus." "the first word read immediately after RAM address set is not outputted, so that it is invalid." p. 78 Figure 7: HEA-HAS 8'h4 8'h04 p. 83 RTNI: Note to Table 55 added. DIVI: "Setting DIVI 2'h0 is inhibited.", note to Table 56 added. p. 86 VEQWI Table 59: 3'h4 Setting inhibited clocks. 4
p. 87 DIVE Table 60: 8-bit, 3 transfers RGB interface 6-bit, 3 transfers RGB interface p. 92 Revised. p. 93 Instruction List: Rev 1.1 p. 94 l.2 the MPU 1.2 the microcomputer
p. 99 "FMARK interface operation" added. p. 117-120 "FMARK Interface" inserted. p. 124 Figure 40, Note 3 to Figure 40: (DB5-0) deleted. p. 127 Unused pins DB11-0 (DB17-6) DB11-0. p. 128 Figure 43: DB5-0 deleted. p. 136-140 (in rev 1.1, FMARK Function) deleted. p. 139 Figure 53: Original image data size image data Original Unused pins 10.
Figure 42: DB5-0, DB17-6 deleted. RIM 010, 110
Rev.1.21 April 9, 2007, page 204 of 205
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R61505U
Rev. Date Contents of Modification p. 154 Note 1: "when using RC element" deleted. p. 158 Figure 72: Shottky diode between VCI-VGH DDVDH VGH p. 159 Figure 73: Shottky diode between VCI-VGH DDVDH VGH p. 160 Table 87: VCI-VGH p. 165 Figure 77: VPP3 DDVDH-VGH VPP3A/VPP3B Drawn by
Approved by
p. 169 Figure 81: RTNI, DIVI are added to Instruction Initial Setting. R19h TBT[1:0] = 2'h0 is added to LCD Power Supply ON Sequence. BT=3'h7 and VC= 3'h6 are added to Power supply user setting. Note 1 is added. p. 171 Figure 82: Power supply user setting added. p. 173 Figure 84 "User setting 1 NL, BP, FP, gamma, RTNI, DIVI setting, others" added next to Initial instruction setting. p. 174 Figure 85 "User setting 1 NL, BP, FP, gamma, RTNI, DIVI setting, others" added next to Initial instruction setting. p. 175 Figure 86 "User setting 1 NL, BP, FP, gamma, RTNI, DIVI setting, others" added next to Initial instruction setting. p. 177 Table 91: Power Supply Voltage 11 VPP3 VPP3A/VPP3B
Rev.1.21 April 9, 2007, page 205 of 205
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